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"!&  M x |& x& |@ " & ? x |@& & x& |?ٙ㿈`>`,` !\#D!\'#`'`\ 8!#dd" ###```""DD#\ 4\   $  '' ``$i $P` =   * %@@ '`@ * %@' `* %@' `* %@' `* %@ '@ * @%@@'6` `* %@@@'&`@+` `* %@@'`@& F    `@& *` %@*@  "@ `@& 0       !`p"`t@x`` ``&  &L' !"@x?\&``㻠  . @" z " ` :  `  : : *  6!! @  !  !!  6` &` &`` &&`&&`&`(&@&`&@:  ` :  :  ` :  &    :  ` :  &`$& & &  &  &`  @"  P @   @& (  # "@ "``6"&" "` @ ( # ?# #  8?# `@ "`?㻀&   ``@`  &`#\\#`!0` B@  . @" @" &@:  ` : : *   6 ` & & && `6   & `& &`&` 6   & & && ' ' 6  & @ #  @&#     # # #   (## #:  ` : &@:  ` :  &&`:  ` :   # $&&&& # @ y&@ @"  ࠔ@   `@& `@ (   #  # ""@("``6"&" "` `@ '`'( """ 8"`"@ܖ"`㿐. @`"    `@&  (`@ ```#```#`&``&`@ ("``6"&" "` `@ '`'( """ 8"`"@ ܖ"`㻈  . @" @" &@:  ` : : *   $ ` & & && `$   & `& &`&` $   & & && ' ' $  4 @ #  @4#     # # #   (## #:  ` : &@:  ` :  &&`:  ` :   # $&&&& # @ y&@ @"  ࠔ@   `@4 `@ (   #  # ""@("``$"4" "` `@ '`'( """ 8"`"@ܖ"`㿈''/uऔ `쉠 B B @BD㿈?@ #F/u, 8g2 g h' '쀦` B B @BD㿐/t【 $ ??㿐㿠㿠Queue full. random.seedr%dw Global placement running time %.2fs, Detailed placement %.2fs Partition %.2fs, bin-annealing %.2fs, cell-annealing %.2fs Error in time() xjyang.cs.ucla.eduER Lab, UCLA%s@%s (%s) %s %s %s %s %s >p>p>p@@YUnknown input format!The number of modules %d doesn't match. Error! The number of modules %d doesn't match. The number of instances %d doesn't match. Error! The number of instances %d doesn't match. The number of pins %d doesn't match. Error! The number of pins %d doesn't match. Terminal numbers are not match!Error! The number of standard cells doesn't match. Circuit statistics(1): Circuit-Name %s # of modules = %d # of instances = %d # of std cells = %d # of I/O pads = %d # of nets = %d # of pins = %d # of pins per cell = %.2f # of pins per std_cell = %.2f # of fanouts per std_cell = %.2f Max # of pins per cell = %d? Circuit statistics(3): Number of nets with %3d pins = %5d (%4.1f, %4.1f)Bcell %s height doesn't match standard height!Number of rows is %d, should be in (0, %d)White space should be on. Circuit statistics(2): Standard cell height = %d Standard cell total width = %d Average standard cell width = %.1f Number of standard rows = %d Row space = %d White space ratio = %.4f Chip size is %d x %d, Aspect Ratio(W/H) %.2f Global bin %d x %d Average #cells per bin %.2f????zG{?QRset chip size for LEF/DEF format.Number of rows is %d, should be in (1, %d)row %d: width (%d) doesn't match chip width (%d)read %d models and %d model-pins (without VDD/VSS) Standard cell height = %.2f Standard cell total width = %.2f Average standard cell width = %.2f Core site width = %.0f Row Utilization = %.2f%% Core Utilization = %.2f%% White space ratio = %.2f%% Chip size is %.2f x %.2f, Area %.2f Aspect Ratio(W/H) %.2f??@Y-fParse error in command line..auxWarning: Inappropriate bookshelf auxilary file name: %s .logr.log%dwLog file %s open for write error. ---------------------------------------------# Log file name: %sLog file %s was closed. # Command line: %s # Host : %s# Date : %s.timeaRunning time: %.2f seconds -qCommand line parse error, around "%s".-it%d-ip-op-temp-fr-count-yal-tw-pin-tran-kb-bin-cbin-cp-pre-net-bal-mov-chrow-res-si-sg-sm-mul-loc-pad-fmt-cr-qua-sp-dis-pn-ry-ti-nr-hm-gr-row-cpl-cpo-cy-co-con-dl-rd-chp-book%s.aux-wb-wbp-wop-spt-fast-ws%fWhite space should be less than 0.20-rsRow space ratio should be in (0.0, 1.0)-crs-fp-gd-pd-pd shouldn't be zero.-at-at should be a positive integer.-ap-au-aub-hu-rb-hr-hr shouldn't be zero.-ca-ra-ci-ex-cc-ce-tmp-do-nl-pt-pc-pi-dc-ln-cutr-tf-fd-xf-defout%s-ze-bt-dp-tp-wa-ga1-ga2-msUnknown option "%s"?ə?Can't determine the cell %d, %s 's model(%s) number.Sorting cells by name......Cells are not properly sorted%s:%u: failed assertion cell.cdoneNFNlargest cell width %d, smallest cell width %d.not enough fake cells Net(%d): %d %s/%sSTANDARDCOREcorePADPARENTFEEDFEEDTHROUGHunkown type %s in line %dUnknown type %dIOBFPIPOPBINPUTOUTPUTUnkown pin type %dTOPBOTTOMLEFTRIGHT Allocate %dK memory for pins of modulesmalloc error Allocate %dK memory for pin delays of modules MPIN converter out of range. Re-allocate %dK memory for %dth block of pins of modules %s:%u: failed assertion model.ccouldn't find pin %s in model %sMDELAY converter out of range. Re-allocate %dK memory for %dth block of delays of modules Error! Pin [%s] can't be found in model %s Pin [%s] can't be found in cell %d, model %d line %d: Pin [%s] can't be found in cell %d, model %d [Mem] Allocate %dK memory for cell delaySuppose to set %d cell delays, only %d indeed.Generating interconnecting nets...... number of nets exceed circuit.net_numNumber of Net lists out of range. Generated %d nets so far......Move nets error! Generate %d nets. number of nets %d dosent's match..netWrite netlist file %s......wOpen file error %sNet %s %d : %d done.Read netlist file %s......rCouldn't find file %s%sNetNet %s %d%s:%u: failed assertion net.c%dNumber of net %d is not expected.doneRead %d nets and %d pins from file.There are %d large nets (number of pins >= 50)Coudn't find pin's fanin!wires: %.0f horizontal and %.0f vertical.Reset all the pins to center-of-cells.Restore all pin locations.Initialize all pin locations.Center Pin WL = %.0fcell %d pin %d (%d,%d)Create %s as the bin wirelength report.file %s open for write error!net %d %s xmin=%d xmax=%d ymin=%d ymax=%d bb=%d malloc error Maximum net crossing across horizontal cuts (hMax) : %dMaximum net crossing across vertical cuts (vMax) : %dThere are %d 1-pin nets. Consider only %d nets out of %dBounding box wirelength in total: %.0fBounding box wirelength of 5%% shortest nets: %.0fBounding box wirelength excluding 5%% shortest and longests: %.0lfBounding box wirelength of 5%% longest nets: %.0lfBounding box wirelength of 10%% longest nets: %.0lf??ffffff??7) @.parrfile open error %sGENR*numrows:%d.gdpN_SC_ROWSRead number of rows = %d from file %s[Mem] Allocate %dK memory for standard rowsmalloc error Sort cells for each row ......done%s:%u: failed assertion row.cRow %d length = %d %.2f%%Max row total-cell-width %d +%.2f%% average %.2f%% chip widthMin row total-cell-width %d -%.2f%% average %.2f%% chip widthMax row width %d %.2f%% chip widthMin row width %d %.2f%% chip width# Maximum row TCW %d (%.2f%% average) (TCW=total-cell-width) # Maximum row width %d (%.2f%% chip width) @Ytoo many cells are not in row center.cell %s (%d) is not in row center.set standard rows ...done.?@YInput format is TimberWolf's format. .statrfile %s open error%snum_stdcellsnum_stdcells:%dnum_instancesnum_instances:%dnum_padsnum_pads:%dnum_netsnum_nets:%dnum_pinsnum_pins:%dnum_modelsnum_models:%d Circuit information: #instances = %d #standard cells = %d #IO pads = %d #nets = %d #pins = %d #models = %d Allocate memory for placer: Allocate %dK memory for modelsmalloc error Allocate %dK memory for cells Allocate %dK memory for pins Allocate %dK memory for netsReading Models.......libLibrary file open error. LIBRARY/*ENDLIBRARYMODEL%s%s%s%sENDMODELThe number of models is out of range. BOUNDARYPINPORTDELAYRead %d models%f%f%s%s%sSyntax error in %dLAYERLAYER %dCAPACITANCECAPACITANCE %fRESISTANCERESISTANCE %fSyntax error in line %d.RISETIME=%fFALLTIMEReading Cells.......cktCircuit file open error. CIRCUITENDCIRCUITINSTANCEThe number of cells is out of range. %s%s%s%s%sDELAY=Syntax error in line %d, no delay information%fDELAY=%fBPin name (%s) too long!number of pins out of range.number of pins %d is out of range.number of pins out of range. %s%smalloc error Input format is YAL. .yal.ctlrfile %s open error %sYALCONTROLENDYALCONTROLSyntax error in %sNMODULESNMODULES %dNTERMINALSNTERMINALS %dNCELLSNCELLS %dNPINSNPINS %dNNETSNNETS %dPADDUMMYPADDUMMY %d %dFILESCircuit information from %s: #models = %d #instances = %d #nets = %d #pins = %d Allocate memory for placer: Allocate %dK memory for models Allocate %dK memory for cells Allocate %dK memory for pins Allocate %dK memory for nets Reading %s......In file %s line %d, line is too long.MODULEENDMODULETYPEDIMENSIONSWIDTHSyntax error in line %dWIDTH %fHEIGHTHEIGHT %fIOLISTENDIOLISTNETWORKENDNETWORKSyntax error in file %s line %ddone/**/ Syntax error in line %d%s%s Model name is too long in line %d Unknown type of module in line %dDIMENSIONS %f%f%f%f%f%f%f%f%s%s%s%s%s%s%f%d%s%s%s%f%f%d%snumber of cells %d is beyond control.ICNCnumber of pins %d is beyond control.rPlacement file(%s) open error.Reading Placement file %s ......%s%s%d%f%f%f%f%d%d Cell %s not found when read placement.done ??wPlacement file open error. Create %s file as result......%s %s 0 %.2f %.2f %.2f %.2f %d %d %%s %%s 0 %%%s %%%s %%%s %%%s %%d %%d %s %s 0 %.0f %.0f %.0f %.0f %d %d done..dispDisplay file %s open error.Created file %s for display......COLOR WHITE SRD %d %d %d %d SRF %d %d %d %d COLOR BLACK SR %d %d %d %d COLOR BLUE COLOR GREEN malloc error COLOR GREY SL %d %d %d %d Display mode is not correct!COLOR RED STR %d %d Number of standard cells = %d, Pads = %d STR %d %d AREA = %d x %d STR %d %d Total WL = %.1f @@?.moveMovement Display file(%s) open error.Created file %s for display. SC %d %d 1 @@.nlstCreated file %s for net infomation......net%5d:%s xspan:%d yspan:%d length:%d numpin:%d done.pthRead file %s for net info......%snet%s%s%s%s%s%s:%u: failed assertion fileio.c%dNet %d not found.Net %d mismatch: bb=%d, length=%dBegin reading I/O pads locations.......padError Pad file. Cell name not found:. ??.rteRouting file %s open for write.Create %s file as routing input file for Labyrinth ......grid %d %d vertical capacity %d horizontal capacity %d num net %d %s %d %d %d %d open file %s to %sreadwriteOpen file error: %sCreate a temperary file for DP: %s%d %d %d Read the temperary file by GP: %s%d %dbin m n doesn't match the current one!Input format: LEF/DEF. open file %s to %srreadwriteOpen file error: %s%sdefNamedefName %slefNamelefName %ssdfNamesdfName %sPre read LEF file: MACRO%s%sPINENDpre-read %d models and %d model-pins[Mem] Allocate %dK memory for modelsmalloc error Pre read DEF file: COMPONENTS%s%dPINS-%s%s%s[Mem] Allocate %dK memory for %d cellsRead LEF file: SITECLASSSIZE%s%f%s%fread %d models and %d model-pins (without VDD/VSS)?DFF?VSSVDDDIRECTIONmodel %s: pin %s: direction unknown!RECT%s%f%f%f%f?model %s's height (%d) is not a multiple of the standard height (%d).model %s's height (%d) is not standard height (%d).check all models --- they have the same height %dDUMMY_INPUTDUMMY_PINDUMMY_OUTPUTafter creating two dummy models: #models = %d, #model-pins = %dRead DEF file: set number of rows to be maximum (%d).DESIGNUNITSDIEAREAROWNETS[Mem] Allocate %dK memory for nets[Mem] Allocate %dK memory for pinsread %d cells.Expect %d cells, read %d cellsread %d nets.Expect %d nets, read %d nets, %d 0-pin netsExpect %d nets, read %d netsExpect %d pins, read %d pins.read %d pads (PINS)Expect %d pads, read %d pads.%s%s%s%dDISTANCEMICRONSUNITS line syntex error.Read UNITS = %dCannot handle: UNITS scaling factor is less than %d%s%s%d%d%s%s%d%d%sread die size %d x %d%s%s%s%d%d%s%s%d%s%d%s%d%d%s%s%d%d%s%s%d%s%d%s%d%dread more than %d rows.Check %d rows:reverse all the rows to get increasing y coords.row 0: origin is not 0.row %d: origin is not 0.row %d: width doesn't match.row %d: rows are not regular (standard cell height).row %d: row space doesn't match.rows are correct.Chip area %d x %d Syntax error in line %d.PLACEDFIXED Syntax error in line %d: expect PLACED or FIXED. Syntax error in line %d: expect '('.%d Syntax error in line %d: expect ')'.NFNSFS Syntax error in line %d: expect N, FN, S or FS. Syntax error in line %d: before ';'line %d: cell %s couldn't be found.Syntax error in line %d: expect '+'.NETOUTPUTINPUTSyntex error in line %d: expect INPUT/OUTPUTUSELAYERSyntax error in line %d, expect '('Syntax error in line %d, expect ')'Syntex error in %d.Unknown Pad direction '%c'Unknown Pad direction '%d'Read %d nets and %d pins from file.There are %d large nets (number of pins >= 50)Pre-read SDF file:(IOPATH(COND pre-read %d IOPATHs.Read SDF file: (DIVIDER(CELL(CELLTYPE(INSTANCE(INSTANCE)line %d: expect ')' after %sline %d: cell %s not found.read %d delays (IOPATHs).Syntax error at line %d: expect (IOPATH.%s%s%s%s%s%sline %d: expecte ')' after %s()line %d: expect '(' around %sline %d: expect a float after '('(%flink all delays (IOPATHs) to cells...cell %s doesn't have delays.okaycell %s model %s: ni=%d no=%d delay_num=%d --- WARNING!Output GCF file ....gcfw gnd!vdd!(ARRIVAL (posedge "CLK") 0.000 11.000 0.000 11.000(DEPARTURE (posedge "CLK") 10.000 10.000 -0.800 -0.800 %s) Output Placed DEF file ....defDEF file name %s doesn't contain .def-dr.defEND COMPONENTScell %s not found.cell %s direction unkown.- %s %s + %s ( %d %d ) %s ; Write DEF file for Capo/MetaPlacer ...-capo.defCOMPONENTS %d ; - %s %s ; - %s %s + FIXED ( 0 0 ) N ; END PINS-merge.defMerge %s and %s to new DEF: %sinput defName doesn't contain .def.qpout.def-qpout.def-qp.deftsmc18.tlfReading timing library file...cellSyntex error at line %d: expect '('.modeldlySyntex error at line %d: expect '_'.(load_axis%f%f%f%f%f%f%fError at line %d: expect 7 numbersError at line %d: expect '('%s%s%s%s%s%s%sLine %d is weird.%fpinLine %d: expect '('.timing_props(pin_cap(Line %d: expect a number.Finish reading %d model delays.%s:%u: failed assertion fixdie.c --> %d (%.2f%%)After dumb spreading BB = %.0f@Y[fixdie] Allocating white space to rows ...Normalized wirelength = %dBinY ttl congestion: max %.2f min %.2ftotal white1 = %.3f, (1-row_util)*row_num=%.3fO???[fixdie] Allocating white space into bins ...malloc error white space assignment mode: %dwhite space is less than 0??Quadratic assignment...[c1,c2]=[%.3f,%.3f], [w1,w2]=[%.3f,%.3f], w=%.3fbin-row congestion: max %.2f, min %.2fcs=%.3f, cq=%.3f, c1=%.3f c2=%.3f w1=%.3f w2=%.3f w=%.3fa1=%.5f a2=%.5f a3=%.2f max point = %.5f, y = %.5fConvex Quadratic: fix w2, extreme c2, recaculate w1:a1=%.5f a2=%.5f a3=%.5fmax point = %.4f, y = %.4fnew w1 = %.5fConcave Quadratic: fix w1, extreme c1, recaculate w2:new w2 = %.5fequation 1: w1=%.3f right=%.3fequation 2: w2=%.3f right=%.3fequation 3: w=%.3f right=%.3frow white space max %.2f%% min %.2f%%BLinear assignment...OBinitialize names buffer.malloc error Impossible, names need so many space(1G)![Mem] All names occupied %dK bytes. fatal: [%s:%s, line %d]fatalmisc.c Program exit abnormally. panic: panicwarning: warninfoinfo1log2() only works for positive power of two values0s%ldD %ldh %ldm %lds Delete large cells (>=100x minimum)...malloc error Minimum cell width: %d Delete %d cells with width %d.ckt.newwFile open error %sWrite %s file.../* Generated automatically, after deleting large cells from newibm */ CIRCUIT %s INSTANCE %s %s cell %d pinnum = %d(%s %s) ENDCIRCUIT .yal.part%s:%u: failed assertion tran.c %s %s %s ; Delete large cells (>=%dx minimum) and models...Altogether delete %d(%d) cells.yal.new.yalr%sNETWORKENDNETWORKMODULE%s%sENDMODULEdoneCouldn't find cell named %sCouldn't find model named %s.myalfile %s open error Create %s file......MODULE %s; TYPE %s; WIDTH %d; HEIGHT %d; IOLIST; %s %c TOP %d 0 METAL2; ENDIOLIST; ENDMODULE; .pyalPrint module information for .yal file TYPE %s; WIDTH %f; HEIGHT %f; IOLIST; %s %c %.1f %.1f 3 POLY ; ENDIOLIST; ? Create YAL format files..... Identify dangle nets and dangle cells....yal.ctl.new.yal.ctlYALCONTROLS; NMODULES %d; NTERMINALS %d; NCELLS %d; NPINS %d; NNETS %d; FILES %s; ENDYALCONTROLS; done./* Automatically generated by Xiaojian Yang */ FEEDTHROUGH p%d %s %.1f %.1f 3 POLY ; TYPE PARENT; IOLIST; ENDIOLIST; NETWORK; %s %s %s ENDNETWORK; ENDMODULE; ?BB_FLAMEPrint module with pin location information file %s %s %s %.1f %.1f 3 POLY ; ?Error! net %s has 0 pin.There are %d neighber nets for net %dchoose two cells between (%d, %d)Coudn't file a pair.Switched %d pairs of cells.Switch cell %d(net %d) <---> %d(net %d)..gdifCreate %s as the routing input file......(gdif (gdifVersion 1 0 0) (comment "Automatically generated by Dragon") (cell:%s INOUTPin type is not in/out for mode %s, assume it's IN (port:%s (layer MET2) (type %3s) (pt 0 0 )) ) (cell:top (comment "parent module") (instance:%s (cellRef %s) (pt %d %d )) (net:%s (portRef %s (instRef %s)) ) ) ) Scaling all cell/model size ...total std width = %dexpected number of rows is %d??>+Bmodel %5s: width %8.2f num_pin %2d pin %8.2fMinimum Pin Density %10.2f (%d-pin cells)O-6l.lef-5l.lef.lefopen file %s to %sreadwriteOpen file error: %sCreate %s as the LEF file......VERSION 5.1 ; NAMESCASESENSITIVE ON ; UNITS DATABASE MICRONS %d ; END UNITS LAYER POLY1 TYPE MASTERSLICE ; END POLY1 LAYER METAL1 TYPE ROUTING ; WIDTH 0.23 ; SPACING 0.23 ; SPACING 0.6 RANGE 10.0 100000.0 ; PITCH 0.56 ; DIRECTION HORIZONTAL ; END METAL1 LAYER VIA12 TYPE CUT ; END VIA12 LAYER METAL2 TYPE ROUTING ; WIDTH 0.28 ; SPACING 0.28 ; PITCH 0.66 ; DIRECTION VERTICAL ; END METAL2 LAYER VIA23 TYPE CUT ; END VIA23 LAYER METAL3 TYPE ROUTING ; PITCH 1.12 ; DIRECTION HORIZONTAL ; END METAL3 LAYER VIA34 TYPE CUT ; END VIA34 LAYER METAL4 TYPE ROUTING ; DIRECTION VERTICAL ; END METAL4 WIDTH 0.44 ; SPACING 0.46 ; PITCH 1.32 ; LAYER VIA45 TYPE CUT ; END VIA45 LAYER METAL5 TYPE ROUTING ; DIRECTION HORIZONTAL ; END METAL5 LAYER VIA56 TYPE CUT ; END VIA56 LAYER METAL6 TYPE ROUTING ; DIRECTION VERTICAL ; END METAL6 LAYER OVERLAP TYPE OVERLAP ; END OVERLAP VIA via1 DEFAULT LAYER METAL1 ; RECT -0.19 -0.14 0.19 0.14 ; LAYER VIA12 ; RECT -0.13 -0.13 0.13 0.13 ; LAYER METAL2 ; RECT -0.19 -0.14 0.19 0.14 ; END via1 VIA via2 DEFAULT LAYER VIA23 ; RECT -0.13 -0.13 0.13 0.13 ; LAYER METAL3 ; RECT -0.19 -0.14 0.19 0.14 ; END via2 VIA via3 DEFAULT LAYER VIA34 ; RECT -0.13 -0.13 0.13 0.13 ; LAYER METAL4 ; RECT -0.19 -0.14 0.19 0.14 ; END via3 LAYER METAL3 ; RECT -0.24 -0.19 0.24 0.19 ; LAYER VIA34 ; RECT -0.18 -0.18 0.18 0.18 ; LAYER METAL4 ; RECT -0.27 -0.27 0.27 0.27 ; VIA via4 DEFAULT LAYER VIA45 ; RECT -0.13 -0.13 0.13 0.13 ; LAYER METAL5 ; RECT -0.19 -0.14 0.19 0.14 ; END via4 VIA via5 DEFAULT LAYER METAL5 ; RECT -0.24 -0.19 0.24 0.19 ; LAYER VIA56 ; RECT -0.18 -0.18 0.18 0.18 ; LAYER METAL6 ; RECT -0.27 -0.27 0.27 0.27 ; END via5 LAYER METAL4 ; RECT -0.24 -0.19 0.24 0.19 ; LAYER VIA45 ; RECT -0.18 -0.18 0.18 0.18 ; LAYER METAL5 ; RECT -0.27 -0.27 0.27 0.27 ; SPACING SAMENET METAL1 METAL1 0.23 ; SAMENET METAL2 METAL2 0.28 ; SAMENET METAL3 METAL3 0.28 ; SAMENET METAL4 METAL4 0.28 ; SAMENET METAL4 METAL4 0.46 ; SAMENET METAL5 METAL5 0.28 ; SAMENET METAL5 METAL5 0.46 ; SAMENET METAL6 METAL6 0.46 ; SAMENET VIA12 VIA12 0.26 ; SAMENET VIA23 VIA23 0.26 ; SAMENET VIA34 VIA34 0.26 ; SAMENET VIA45 VIA34 0.26 ; SAMENET VIA56 VIA34 0.35 ; SAMENET VIA45 VIA34 0.35 ; END SPACING SITE core SIZE 0.66 BY 5.04 ; CLASS CORE ; SYMMETRY y ; END core MACRO %s CLASS CORE ; SIZE %.2f BY %.2f ; ORIGIN 0.00 0.00 ; SYMMETRY x y ; SITE core ; PIN P%d DIRECTION INOUT ; USE SIGNAL ; PORT LAYER METAL1 ; RECT %.4f %.4f %.4f %.4f ; END END P%d END %s END LIBRARY delete %d empty macros (0 pin).A?d.defCreate %s as the DEF file......DESIGN %s ; UNITS DISTANCE MICRONS %d ; END DESIGN delete %d dangle cells.COMPONENTS %d ; - %s %s ; END COMPONENTS PINS %d ; - %s + net %s ; END PINS NETS %d ; - %s ( %s P%d ) ; END NETS Assign I/O pad locations...done.Pad width are not identical!!!!!!!!!!!!!!!!!!!!!!!Check pad width finished.pad.%s.pl1wFile open error %s Create %s as pad location file......%s %s 0 %d %d %d %d %d %d Number of rows is invalid....gdpGDP file open error %sCreate %s as gdp file......N_SC_ROWS: %d N_BIN_ROWS: 16 N_BIN_COLS: 16 malloc error Adjust right side I/O pads locations... Maximum row length is %d, +%.1f%%@Y.con.newfile %s open error Write %s as pad/timing constraints file.Pad %s row number incorrect.PAD %s RESTRICT SIDE %c SIDESPACE %8.3f PATHCONSTRAINT %s/%s %s/%s (999) pad..pl1Write %s as pad location file for Dragon.Input format: GSRC bookshelf. .aux.out.auxOptions error, shouldn't read aux file.rfile %s open error %sRowBasedPlacementSyntax error in %s, expecting RowBasedPlacement.Syntax error in %s, expecting ':'.Syntax error in %s:%s, no extension file name.nodes.nets.wts.scl.plSyntax error in %s:%s, file extension name invalidReading %s......UCLANumNodes Allocate %dK memory for cellsmalloc error NumTerminalsNumber of nodes wasn't specified.%s%s%s%sterminal%fSyntax error at line %d: expect two numbersNumber of nodes %d doesn't match.Number of I/O pads %d doesn't match.Finish reading nodes file.NumNets Allocate %dK memory for netsNumPins Allocate %dK memory for pinsNetDegreenet%.5d%s%s%s%f%f:cell %s couldn't be found.pin%.6dread net file done.Number of net %d is not expected.Number of net %d is not expected, out of rangeNumber of pin %d is not expected.Number of pin %d is not expected, out of rangeRead %d nets and %d pins from file.There are %d large nets (number of pins >= 50)?Right now we don't need to read weights file %sReading layout file %s ......NumrowsCoreRowNumber of rows %d out of range.CoordinateHeightSitewidthSitespacingSubrowOrigin%s%s%s%s%s%s%dNumsitesSyntax error in line %dFinish reading layout file.Number of rows read %d is not matching.Row %d width %d is not consistant.Row %d height %d is not consistant.Row space between row-%d and row-%d is not consistant.Row %d start(SubrowOrigin) %d is not consistant.Row %d SiteWidth %d is not consistant.Reading placement file: %s%s%f%f%s%sFinish reading placement file.?Pad %s row number error%s is not a placement file name(.pl)_Dragon.plwWrite bookshelf format Place file %s......pl%%8s%%12%s%%12%s : N done.%dfNeed bookshelf format to change row spacing.There's no need to change row spacing..newSorting pins by cell number ......done. Allocate %dK memory for models Allocate %dK memory for pins of models Allocate %dK memory for pin delays of models mod%dSyntax error in line %d, expecting ':'Syntax error in line %d, expecting a number.Set chip dimensions......Number of rows is %d, should be in (0, %d)cell %s height doesn't match standard height!cell standard height %d doesn't match row standard height %d! Circuit statistics(0): Standard cell height = %d Standard cell total width = %lld Average standard cell width = %.1f Number of standard rows = %d Row space = %d Site width = %d Chip size is %d x %d Aspect Ratio (W/H) %.2f White space %.2f%c Global bin %d x %d??@Y.whiteRead white space file %s......Write white space file %s......%.2fOutput format: GSRC bookshelf. DEF file name wrong.%s-cu%sWrite bookshelf format auxilary file %s......%s_DG_R%d_WS02%s.nodes%s.nets%s.wts%s.pl%s.scl%s-cu%s.pl%s-cu%s.sclRowBasedPlacement : %s %s %s %s %s DoneWrite bookshelf format file %s......nodes NumNodes : %d NumTerminals : %d %s %.1f %.1f terminal wts %s %d nets NumNets : %d NumPins : %d NetDegree : %d %s %2s : %d %d %s %2s : 0.5 0.5 scl NumRows : %d No white space setup! Set white space 0CoreRow Horizontal Coordinate : %d Height : %d Sitewidth : %d Sitespacing : %d Siteorient : %d Sitesymmetry : %d SubrowOrigin : %d NumSites : %d End ?# Created : # User : # Platform : UCLA %s 1.0 %s%s# Tool : Dragon %s # Command line : %s # # Circuit %s # Models %d # Cells %d # Standard cells %d # I/O pads %d # Nets %d # Pins %d # Avg pins/cell %.2f # Std cell height %d # Total cell width %lld # Avg cell width %.1f # Number of rows %d # Row space %d # Row Utilization %.2f%% # Core Utilization %.2f%% # White space %.2f%% # Chip size %d x %d # Aspect Ratio(W/H) %.2f # Total Wirelength %.0f # Running Time: %.2f seconds @Y?%s:%u: failed assertion timing.cwhat happened?Calculate wire delays for all net segments...Duplicated source pins in one net (%s)No source pin for net %sdone.?Calculate all cell delays....GateDelay: cell %s: pin pair (%s %s) couldn't be found.u3\/U\/u1_1/U362U9447YBPin pair delay: (%s:%s)-->(%s:%s): %.2f nslongest path from p1->p2: %.2f.conopen file %s to %srreadwriteOpen file error: %smalloc error Allocate %dK memory for timing constraint pathsPATHCONSTRAINTPATHCONSTRAINT %s %s (%f)Syntex error in .con file.cell name not found (%s).Read %d timing constraints. extract pin name error (%s)Longest path from %s to %s (%d pins): %s --> %s: delay = %.2ftotal gate delay = %.2f, net delay = %.2f net %s len %d gate-delay = %.2f, net-delay = %.2f, total-delay = %.2f Violation = %.2fTotal timing violation = %.2fcdelay %d delay <=0ARGHHH!Maximum longest path has a delay of %.2fnsthere is no path from %s:%s to any PO/FFLP from %s:%s is to %s:%s: %.2f(%.2f/%.2f/%.2f)Timing analysis for current placement. find %d terminal pins. sort terminal pins by arrival time...maximum delay = %.2f[Mem] Allocate %dK memory for timing constraint pathsBuild %d critical paths...Maximum delay = %.2fmin_require shouldn't be < 0. (1)min_require shouldn't be < 0. (2)OLink all cell delays to corresponding pins...cell delay cannot be found.Finish assigning weights, max=%d min=%d.Relax: %s:%s --> %s:%sDFS traverse pin graph...ushpcatch_reg\[7\]U675 PIN %s:%s there are %d pins in topo list.7w7Q9;9@Allocate %dK memory for pin-edgesmalloc error Re-allocate %dK memory for pin-edgesBuild longest path from %s:%s to %s%s (%d pins): Path %d: %.2f (%.2f/%.2f/%.2f)Allocate %dK memory for net path-edgesSlack stats: %.2f(%.2f %d %.1f%%)@YThere are %d nets with 1 pin.malloc error finish iteration %d, mps=%d%s:%u: failed assertion slack.cmaximum delay = %d%d slack to %d nodes:%d(%d),%d,open file %s to %stemp-slackwrreadwriteOpen file error: %s%d maximum slack is %d (>=200)%5d%3d A net slack is out of range.slack %2d: num %5d avglen %7.0f?Total delay bound vio = %.0fTotal %d/%d/%d nets have too large/small/medium bounds.hierarchy%s:%u: failed assertion bound.copen file %s to %swrreadwriteOpen file error: %s%d %derror!!!%6d%8d%8.0f%8.1f@@?@malloc error ============================================================================Best fit-quality = %.4f, Rent exponent(p) = %.3f, Interception(T) = %.3f level %d: FIT: result %.3f a=%.3f fit_Q=%.4f chi2=%4f Input Rent Exponent r : %fDonath Wirelength Est. = %.2fDavis Wirelength Est. = %.2f 2:Dirk Wirelength Est. = %.2f Input Rent Exponent r : Donath length r = 0.5!!!!!!!!!!!!!!!!!! ??@?@"@@@ r = %.2f, H = %f numnets=%d, avgL1=%f, avgL2=%f, L=%f ???zG{level %d, %d L1=%.3f, L2=%.3f @@@? Ra=%f, Rb=%f R(r) = %f ?@@@?@@?@?@?@@@? ???UUUUUU?@?UUUUUU?@@@@@@Input Partitioning Rent exponent: Input Placement Rent exponent: Input #gates: %dlogb1 = %.2f alpha = %.2f ???????@@@??Invalid arguments in routine gammqa too large, ITMAX too small in gcf?qI@9HK  B`>! vx less than 0 in routine gsera too large, ITMAX too small in routine gser???>! v@?? ?@ '3.01-hdragon.padRead pad file successfully.Use "-cp" option to specify vertical/horizontal capacities.Skip congestion reduction.Use "-cbin" option to specify global bin grids..pl1.newDragon terminated successfully! Running time: %.2f secondsInitial wirelength = %.0f.gp0.gp%dx%dBsimulated annealing at %d x %d.gp%dx%dafter set cell at bin center BB=%.f.gpAfter global placement wirelength = %.0fNormalized wirelength = %d.gp1?After allocate white space wirelength = %.0fAfter set bin center wirelength = %.0fDetailed Placement WL improvement = %.2f%cAfter re-arrange pads total wl = %.0f@Y DRAGON %s Copyright (c) 2001-2002 ER Lab Computer Science Department University of California, Los Angeles Please check http://er.cs.ucla.edu/Dragon for update. please report problems and bugs to xjyang@cs.ucla.edu Usage: dragon [-f aux_file | -q config_file | design-name] [-options] aux_file: bookshelf format auxilary file name; config_file: LEF/DEF format config file name; options: -tw TimberWolf format input; -yal YAL format input (with -row or .gdp file); -fd Fixed-die placement (for bookshelf or LEF/DEF format only); -dp Detailed Placement (greedy improvement) ; -row number of rows (for TimberWolf/YAL format only); -fast fast mode (worse quality); -rs row_spacing 0.0-1.0 (from 0 to standard cell height); -dis creates a display file(.disp), use pdisp to display it; -pc center-of-cell for .pl file in bookshelf; -con congestion reduction as the post-processing step; -cbin m n bin grids for congestion reduction; -cp v h vertical/horizontal edge capacities for congestion reduction; Output file: TW/YAL format: circuit.pl1.new Bookshelf: circuit_Dragon.pl Examples: dragon -f ibm01.aux (Bookshelf format, default options) dragon -f ibm01.aux -fast (Bookshelf format, fast mode) dragon -q config -fd (LEF/DEF format, fixed-die mode) dragon -f ibm01.aux -fd (Bookshelf format, fixed-die mode) dragon ibm01 -yal (YAL format) dragon ibm01 -tw (TimberWolf format) dragon ibm01 -book (Bookshelf format) dragon -f ibm01.aux -con -cp 12 14 -cbin 64 64 (congestion post-processing) #Rows=%d, Ending global placement level: %d x %d, %.2f cells/bin@@333?       use -tmp n option: 0<=n<=6!mapping error!Detailed placer only supports Bookshelf or LEF/DEF format.After resolve overlap total wl = %.0fAfter local improvement: WL = %.0f WL = %.0fIter%2d: switch try %5d accept %4d shift try%4d accept%2d wl = %.0fBegin flipping only......wl=%.0f Iter %d: flip %d, wl = %.0fAdjust row balance...malloc error .whiter%s file not found, assume white space = 1%%%f %5d moves, wl=%.0f, balance=%4.2fFor balance altogether %d moves were accepted@Y.cellWrite cell width to file %s......wOpen file error %ssort %5d, cell %5d, name %10s model %10d, width=%6d doneNet has %d pins = %dCheck cell row number...Cell %d row=%d, but it is in row %dRow %d contains no cell, invalid for DPRow checking passed.Need specify -bin M N#rows=%d, N=%d, Not match, no pre-processAfter first spread Wirelength = %.0fAfter second spread Wirelength = %.0fNo -bin option! Auto detect global bins...After permutation wl = %.f Average number of cells per bin = %.2fMaximum number of cells per bin = %dMinimum number of cells per bin = %d%s:%u: failed assertion dpfun.cafter bin center: wl = %.f altogether %d large bins cannot be permutated.Too big num %dbin (%d,%d) contains no cell!only %d cells are reconsidered in pre process (should be %d)total %d cells were changed x, (nStd=%d)?Total cell movement = %8.0fAverage movement per cell = %8.0fAverage width per cell = %8dPad %d has more than one pin.Pad %d contains more than one(%d) pin!!!there are %d pure nets out of %d (%.2f%c)There are %d long netsLongest length is %dNet %d reduce from %d to %d, wl=%.0f%2d: acc %4d long %d wl=%.0fTo reduce %d longest net by %d%c, %d tried and %d acceptedWilrelength increase %.6f%c@@?@YThis net %d cannot be reducedplace.scriptNRow = %d, cannot use automatical script generator.Write place.script file......#!/bin/sh CIRCUIT=%s NROW=%d QUAL=%d BASEDIR=/homes/xjyang BINDIR=${BASEDIR}/bin PAD=${BINDIR}/pad GP=${BINDIR}/gp0.2b DP=${BINDIR}/dp ATT0=`expr $QUAL \* 1` ATT1=`expr $QUAL \* 2` ATT2=`expr $QUAL \* 3` ATT3=`expr $QUAL \* 6` TEMP=100 AP=30 FROZEN=5 echo "---`uname -n` $CIRCUIT GP ---" >>$CIRCUIT.time if [ -r pad.$CIRCUIT.pl1 ] then echo "N_SC_ROWS: $NROW" > $CIRCUIT.gdp else echo "Generating I/O Pad locations......" $PAD $CIRCUIT -yal -cpo -row $NROW fi echo "Begin global placement......" echo "Begin detail placement......" $DP $CIRCUIT -yal -res -loc -temp 30 -count 5 -cr 10 -dis -row $NROW done.$GP $CIRCUIT -PAR READ -PAD PL1 pad.$CIRCUIT -o PL1 $CIRCUIT -wl -ub 1 -hmwgts -frozen $FROZEN -ap $AP -noroute%s%s-ip pl1 -hmetis -split %d -bin -b mn %d %d -temp $TEMP -att $ATT%d -pp 3 %s Should use -cbin argument!after snap: WL = %.f N-WL = %dafter permutation process: WL = %.f N-WL = %dNormalized WL = %dNeed to specify global grid using -bin.Bad hmetis mode, check command line arguments. hMetis partitioning create a initial placement......Malloc error in hMetisPartition(). Partitioning errordone?hMetis partitioning (with pads) create a initial placement......Right now we must start from 2 x 2 bins.?number of partitions should be 4.Begin QUADRISECTIONALLY VERTICALLY HORIZONTALLY splitting global bins with terminal propagation with timing consideration Successful bin splitting: %d x %d%s:%u: failed assertion part.ctarget (%.2f)should be less than 0.5!?malloc error ?.rentwFile open for write error %sWrite congestion estimation file %s.......tbWrite #terminals per cell file %s......(%d,%d) --- %5.2f done.malloc error ---------------------------- -bin(%d, %d): #vertices = %d, #edges=%d (%d, %d): #vertex=%d, #edges=%dnparts netcut %d %d %d %d Partition: vertex=%d, edge=%dWrite rent's rule point file %s......Level %d, instance %d: cut = %d Level %d Average_cut = %.1f Average_ncell = %.2f %.1f%.0f Altogether save %d points for linear regression. (%d ).congrFile open for read error %sRead congestion estimation file %s......%fdoneMax congestion (%d,%d) = %.2fMin congestion (%d,%d) = %.2fMove %d cells from (%d,%d) --> (%d,%d)?? Assign weight for each nets...... Total %d internal nets and %d external netsCongestion information --- Number of nets:%5d.ceRead %s file as the congestion estimation......Open file error %sroute-est Bin interconnect sum:%8.2f%10.5f Write %s file as the routing estimation......Done Bin routing probabilities:rho.dat%8.3f%d %d %f ?.pl1Depth %d, Bin (%d,%d) Average_enet = %.1f bin (%d, %d): cut = %dLevel %d (%d x %d): Average cut = %.1f.lspaWrite xlisp data points file %s...... (def x%d (list %.3f )) (def y%d (list (def myplot (plot-points x%d y%d)) (send myplot :add-points x%d y%d) (send myplot :abline %.4f %.4f) Fast Rent Exponent Extraction for Bin (%d, %d)malloc error Adjust ADD_NET constant or something is wrong.Adjust ADD_PIN constant or something is wrong. Sample Circuit: expected nnet = %d, real nnet = %d Sample Circuit: expected npin = %d, real npin = %dVERIFYING.........Net Pin Number Distribution Comparison:---------------------------------------------------------Real Sample Percentage%.2f %d %.2f?E nhedges = %d, _sc.nnets = %dBegin recursively bipartitioning sample circuitLevel %d, instance %d: cut = %d Level %d Average_cut = %.1f Average_ncell = %.2f %.1fAltogether save %d points for linear regression. total_net = %d (%d )?Annealing is done! Total number of moves: %d Wirelength = %.f************* Begin annealing procedure ************ANNEALER WARM-UP: hold temp, adjust cost factorsinitial stdObjective=%finitial TEMP = %.0f, AP = %.4f, ATT = %dRow UB = %.2f, Bin UB = %.2f net-cut (external nets) = %dIter Temp AP Try Gen Acc totCost WL begin temperature decline...@Y@"?? %d %7.3f %8.6f %d %d %d %10.f BB=%.f%s:%u: failed assertion annealer.c@o@?p =q@b?333333@I?ffffff@$?홙?`bM??PbM?陙?@bM?? Multi-shrink: gen %d try %d acc %d?@Y?@YColumn adjustment at global bin %d x %d. before column adjustment: WL = %.0fmalloc error after column adjustment: WL = %.0fMove %d cells from (%d,%d) ---> (%d,%d) Move cells out of (%d,%d)gain%d Move Net(%d): c(%d) WL = %.0f ---row adjust--- wirelength = %.0f GREEDY: %d %d %d %.fRow unbalance ratio is too tight! Can not get a legal placement!Set row unbalance ratio to %.1f%%@Y? ?G?@Y?Bin dimention (m, n) should be positive integers.malloc error [Mem] Allocate %dK memory for %d global binsCouldn't assign a number of row for bin. Check -bin m n!?%s:%u: failed assertion bin.c?some thing wrong in sort cell for rows.From the first row bin_m=%d, but this row (%d) bin_m=%dAuto-dected global bin (%d,%d)Re-Snap cells into bins......cell %d[%s] is not in chip area. bin grid = (%d, %d), set to (%d, %d) doneSnap cells into bins while keeping their old sequence in row... %d, ===================================== CELL DISTRIBUTION %d x %d -%5d %d after accept %d: wl = %.0f ?Before greedy improve wl = %.0f Iteration %d wl = %.0f?Before single cell greedy improve wl = %.0f?Before single cell greedy improve wwl = %.0f Iteration %d wwl = %.0faccept !After single cell greedy improve wwl = %.0f??There are %d cells to be moved?Bin external nets: Total = %d, Max = %d, Average = %.2fCache memory exceeds maximum number! %dM > %dM[Mem] Allocated %dK memory for bin external listBin external net-list: Real: total = %d max = %d average=%.1fAdjust bin grid according number of rows: %d x %d ==> %d x %d No need to adjust bin according to number of rows. They are the same. After first adjustment: wirelength = %.0f after migration wirelength = %.0f? %d x %d Row width distribution %.4f --- %.4f %d x %d Bin width distribution %.4f --- %.4f %d x %d Bin c_num distribution %6d --- %6d Hey, N is too small!BLACKREDBLUEGREENYELLOWCYANGREYalleviateestimatepathmgryan1Success! .congrfile %s open error Read congested file %s......Output for vEdges:%dOutput for hEdges:vThresholdmaxVCongestioncongested string read error.= %dhThresholdmaxHCongestiondone..cmapRead Ryan's congestion map file %s......%d%dbin grid from cmap file doesn't match -bin!V-Cong: Min=%d, Max=%d, Ave=%.1f, Ttl=%dH-Cong: Min=%d, Max=%d, Ave=%.1f, Ttl=%d VC HC---------- %2d %2d V-Cap = %d, H-Cap = %d V-OF = %d, H-OF = %d, Total OF = %d@?@S33Identify congested bins......avg_vcon = %.2f, avg_hcon = %.2fCalculate bin congestion degree ......Bin congestion max %.3f min %.3f?%s:%u: failed assertion rcong.c.disprwDisplay file %s open error.Created file %s for congestion map display......COLOR WHITE SRD %d %d %d %d SRF %d %d %d %d COLOR BLACK SR %d %d %d %d COLOR GREY SL %d %d %d %d STL %d %d (%d,%d) COLOR RED @@?.dispcCOLOR %s < %.1f > %.1f %.1f - %.1f STR %d %d %s @@?.cunitfile %s open error.%f%fRead unit congestion %.1f and %.1f to file %s%f %fWrite unit congestion %.1f and %.1f to file %smalloc error .grFile %s was opened for reading routed path...... file contains %d lines Allocate %dK memory for routed path.Reading path file....nnnn %sNet name %s unkown!This is not enough!hehe %d %dveve %d %dWierd line in the file: %sRouting memory out of range! Total edges %d, horizontal %d, vertical %d Net %s unrouted.Altogether %d unrouted nets.Analyzing routed wirelength.... Total bounding box wirelength = %d, routed wirelength = %d %4d %2d-terminal net: in_bb max %.3f min %.3f avg %.3fplot1%.4f %.4f wierd. %4d good nets with average congestion %.3f %4d bad nets with average congestion %.3f==== Two-terminal nets classified ==== ==== congested threshold = %.2f ==== Type %d: count %d avg=%.3f?@Yuse -tmp x to represent congestion thresh hold.weird.@Y?zG{Bin congestion max %.3f min %.3f avg %.3f?????1?*?nulldonecplex.solCPLEX solution file (%s) open error!NAMEENDDATASECTION 2 %c%d%s%s%f%s%dcplex solution file error 1!solution_collecta%f ?Expansion Plan: area %2d: (%2d,%2d)-(%2d,%2d) + %d/%d@A@Afile: %s, mode: %s, [%s] Partitions[B]: [%6d,%8d] [%6d,%8d], Initial Cut: %8d [%d] [%d] Partitions: [%6d,%8d] [%6d,%8d], Initial Cut: %8d [%d] [%d %d] Gains from moving %8d from %2d: %4d, Newcut: %d [%6d %6d] Minimum Cut: %8d at %5d [%6d %6d] Partitions2: [%6d,%8d] [%6d,%8d], Initial Cut: %8d [%d] [%d %d] Gains from moving %8d from %2d: %4d, Newcut: %d [%6d %6d %6d] Minimum Cut: %8d at %5d [%6d %6d] Partitions: [%6d,%8d] [%6d,%8d], Initial Cut: %8d [%d] [%d] Gains from moving %8d from %2d: %4d, Newcut: %d Minimum Cut: %8d [%8d] at %5d [%6d %6d] Partitions: [%6d,%8d] [%6d,%8d], Initial Cut: %8d [%d] [%d] Gains from moving %8d from %2d: %4d, Newcut: %d Minimum Cut: %8d [%8d] at %5d [%6d %6d] 1-way Partitions: [%6d %8d %8d] Initial Cut: %8d [%d] [%d %d] Gains from moving %8d from %2d: %4d, Newcut: %d Minimum Cut: %8d [%8d] at %5d [%6d %6d] [%d] Fixing failed: %d %d %d Bisecting a hgraph of size [vertices=%d, hedges=%d, balance=%4.2f] Cut of trial %4d: %6d [%d, %d] [%4.2f] Cut of trial %4d: %6d [%4.2f] The mincut for this bisection = %d, (average = %3.1f) (balance = %4.2f) Wrong cut! %d %d [%d (min = %d)] ---------------------------------------------------------- [%6d %6d %6.2f %6.2f %6.2f %6.2f, %6d %6d %6d %6.2f] [%6d %6d %6.2f %6.2f %6.2f %6.2f, %6d %6d %6d %6.2f] Slow progress in coarsening. Aborted at %d nodes Partitions: [%5d,%5d], Balance: [%3.2f, %5d,%5d], Init Cut: %5d, Init SOED: %5d Moving %6d[%3d] (%3d -> %3d) [%4d %4d %4d %4d] %5d %5d Cut: %8d, SOED: %8d, Nmoves: %3d, Pwgts: [%6d %6d] Partitions: [%5d,%5d], Balance: [%3.2f, %5d,%5d], Init Cut: %5d, Init SOED: %5d Moving %6d[%3d] (%3d -> %3d) [%4d %4d %4d %4d] %5d %5d Cut: %8d, SOED: %8d, Nmoves: %3d, Pwgts: [%6d %6d] Partitioning a hgraph of size [vertices=%d, hedges=%d, balance=%4.2f] Cut/SOED of trial %4d: %6d %6d[%d, %d] [%4.2f] Cut/SOED of trial %4d: %6d %6d [%4.2f] The %s for this partitioning = %d, (average = %3.1f) (balance = %4.2f) [%d %d (min = %d)] %d-way initial %s: %d Timing Information --------------------------------------------------------- Multilevel: %7.3f Coarsening: %7.3f Initial Partition: %7.3f Uncoarsening: %7.3f Aux1: %7.3f Aux2: %7.3f Aux3: %7.3f Aux4: %7.3f Refinement: %7.3f Initialize: %7.3f Iterate: %7.3f Wrap Up: %7.3f Total: %7.3f -------------------------------------------------------------------------------------------------------------------------------------- [%6d %6d %6.2f %6.2f %6.2f %6.2f, %6d %6d %6d %6.2f] [%6d %6d %6.2f %6.2f %6.2f %6.2f, %6d %6d %6d %6.2f] ----------------------------------- Slow progress in coarsening. Aborted at %d nodes %5d %5d %5d Bestcut Icut: %5d ^d s _ _, _(NNOO _00<0H0T0`0l0x00000000000000 0,080D0P0\0h0t0000000000000~0{0x(0u40r@0oL0lX0id0fp0c|0`0]0Z0W0T0Q0N0K0H0E0B0? 0<09$0688  ^ 8  o^ooX0 oo [0 _d@S v UW+6V@8;Lƿ4̌?Ssؾ֡>?L??33@ff@&ff@333@L>?L??@@@333@L< <<<<;;;;Nparts should be at least 2. UBfactor should be between 1 and 49. Nruns should be at least 1. Ctype should be between 1 and 5. Rtype should be between 1 and 3. Vcycle should be between 0 and 3. Reconst should be between 0 and 1. Fixed should be between 0 and 1. HMETIS: graph->cellwgtHMETIS: graph->netwgtHMETIS: graph->netptrHMETIS: graph->netindNparts should be at least 2. UBfactor should be between 1 and 49. Nruns should be at least 1. Ctype should be between 1 and 5. Rtype should be between 1 and 3. Vcycle should be between 0 and 3. Reconst should be between 0 and 1. Fixed should be between 0 and 1. HMETIS: graph->cellwgtHMETIS: graph->netwgtHMETIS: graph->netptrHMETIS: graph->netindHMETIS: graph->cellwgtHMETIS: graph->netwgtHMETIS: graph->netptrHMETIS: graph->netindBucketSortKeysInc: countsCreateCoarseHGraph: graphMemory allocation failed for %s. Requested size: %d bytes Unknown refinement type: %d AllocateRefinementMemory: whereAllocateRefinementMemory: gainAllocateRefinementMemory: ndeg[0]AllocateRefinementMemory: ndeg[1]FM_Refine: permFM_Refine: permFM_Refine: movedFM_Refine: swapsFM_Refine: permFM_Refine: movedFM_Refine: swapsFM_Refine: permFM_Refine: movedFM_Refine: swapsFM_Refine: permFM_Refine: movedFM_Refine: swapsFM_Refine: permFM_Refine: movedFM_Refine: swapsFM_Refine: permComputePartitionParams: gainComputePartitionParams: ndeg[0]ComputePartitionParams: ndeg[1]PQueueInit: queue->nodesPQueueInit: queue->bucketsPQueueInit: queue->heapPQueueInit: queue->locatorPruneHGraph: snetptrPruneHGraph: snetindPruneHGraph: sgraph->netwgtPruneHGraph: sgraph->cellwgtCreateIncidentHGraph: incptrCreateIncidentHGraph: graph->incindCreateIncidentHGraph: adjwgtCreateIncidentHGraph: graph->edgewgtSeparateIslands: ncellsSeparateIslands: auxSeparateIslands: graph->islandmapCombineIslands: imapCombineIslands: auxMultilevelPartition: labelMultilevelPartition: kpwgtsorgpartMultilevelPartition: labelMultilevelPartition: fpartMultilevelPartition: kpwgtsMLRB: bisectionHypergraph_Bisection: parts[i]Hypergraph_Bisection: whereSplitGraphPart:renameSplitGraphPart: snetptr[0]SplitGraphPart: snetind[0]SplitGraphPart: snetwgt[0]SplitGraphPart: slabel[0]SplitGraphPart: scellwgt[0]SplitGraphPart: snetptr[1]SplitGraphPart: snetind[1]SplitGraphPart: snetwgt[1]SplitGraphPart: slabel[1]SplitGraphPart: scellwgt[1]SplitGraphPart: lgraph->netptrSplitGraphPart: lgraph->netindSplitGraphPart: lgraph->netwgtSplitGraphPart: rgraph->netptrSplitGraphPart: rgraph->netindSplitGraphPart: rgraph->netwgtCoarsen: htableCoarsen: permCoarsen: vpairsUnknown matching type! %d CCoarsen: cwhereMatch_Edges: graph->mptrMatch_Edges: graph->mindMatch_Edges: graph->cellmapMatch_Edges: graph->mptrMatch_Edges: graph->mindMatch_Edges: graph->cellmapMatch_EdgesStars: wgtsCompressFixedCells: graph->mptrCompressFixedCells: graph->mindCompressFixedCells: graph->cellmapProjectFixedCells: imapUnknown refinement type: %d AllocateRefinementMemory: whereAllocateKwayRefinementMemory: kpwgtsAllocateKwayRefinementMemory: nrinfoAllocateKwayRefinementMemory: crinfoAllocateKwayRefinementMemory: nrdataAllocateKwayRefinementMemory: crdataRefineKway_Random: permRefineKway_Random: markerRefineKway_Random: updindRefineKway_Random: permRefineKway_Random: markerRefineKway_Random: updindHypergraph_Bisection: parts[i]Hypergraph_Bisection: wheremincutminsoedComputeBalanceKway: kpwgtsInitPartitionKway: bestwherecutsoedhtableCoarsen: htableCoarsen: permCoarsen: vpairsUnknown matching type! %d Match_Edges: graph->mptrMatch_Edges: graph->mindMatch_Edges: graph->cellmapMatch_Hedges: graph->mptrMatch_Hedges: graph->mindMatch_Hedges: graph->cellmapHGraphMatch: graph->mptrHGraphMatch: graph->mindHGraphMatch: graph->cellmapHGraphMatch: graph->cellmapHGraphMatch: graph->mptrHGraphMatch: graph->mindMatch_Edges: graph->mptrMatch_Edges: graph->mindMatch_Edges: graph->cellmapMatch_EdgesStars: wgtsCreateCoarseHGraph: graph->netmapCreateCoarseHGraph: htableCreateCoarseHGraph: coarser->netptrCreateCoarseHGraph: coarser->netindCreateCoarseHGraph: coarser->netwgtCreateCoarseHGraph: coarser->edgewgtCreateCoarseHGraph: candCreateCoarseHGraph: dnetptrCreateCoarseHGraph: dnetindCreateCoarseHGraph: dnetwgtCreateCoarseHGraph: dnetmapCreateCoarseHGraph: dseenCreateCoarseHGraph: coarser->incptrCreateCoarseHGraph: coarser->incindCreateCoarseHGraph: coarser->cellwgtCreateCoarseHGraph: coarser->adjwgtCreateCoarseHGraph: candCollapseSameHEdges: dnetptrCollapseSameHEdges: dnetindCollapseSameHEdges: dnetwgtCollapseSameHEdges: dseenRandom_FMPartition: permRandom_FMPartition: graph->where ^Xp    O [ [0 ^d _( _ _ _ _ s{$& < H W _0e _s s} _ _ _, _(  Θ  H !' 6<)P K _<V]8 ltM@ `  s  s s݄ d  uT s - uL3 uP9@ _DH uXPT _fT u{C V  vX  ,   ) X0 _H07$ FO- ^f> u|   # Z up    \$ `-6=FNW\en{ d h@ &@  @ _,@  %N +N 1;l BO HO NY _ft | _l  _  _`  M  H   &| 7w K8 d$ s z yT d [ h  4 <l d  _\ ˼ ) : C| L U pX$@ g (X s| 0 @ E A T\ d t Et  ߴ4  %O . = Q \Vc  jmH rl y _  tix  Wl OT  [x Yt . 0 1` -e  B y M  TZ [ ]| b lt< } \  z4 l   ݄ ; , ] T & 4 +p H N۴ _y@@ n"l` |  d   $ \p { $4( Yt {$  d \xP Y ( z 2 Fl X k(p T H s,h _0 XX [0 > L   lh ) 7- > X$ ` , z? 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WorkShop Compilers 5.0 Alpha 03/27/98 Build as: WorkShop Compilers 5.0 Alpha 03/27/98 Build @(#)SunOS 5.8 Generic February 2000as: WorkShop Compilers 5.0 Alpha 03/27/98 Build GCC: (GNU) 2.95.3 20010315 (release)as: Sun WorkShop 6 99/08/18 GCC: (GNU) 2.95.3 20010315 (release)as: Sun WorkShop 6 99/08/18 GCC: (GNU) 2.95.3 20010315 (release)as: Sun WorkShop 6 99/08/18 GCC: (GNU) 2.95.3 20010315 (release)as: Sun WorkShop 6 99/08/18 GCC: (GNU) 2.95.3 20010315 (release)as: Sun WorkShop 6 99/08/18 GCC: (GNU) 2.95.3 20010315 (release)as: Sun WorkShop 6 99/08/18 GCC: (GNU) 2.95.3 20010315 (release)as: Sun WorkShop 6 99/08/18 GCC: (GNU) 2.95.3 20010315 (release)as: Sun WorkShop 6 99/08/18 GCC: (GNU) 2.95.3 20010315 (release)as: Sun WorkShop 6 99/08/18 GCC: (GNU) 2.95.3 20010315 (release)as: Sun WorkShop 6 99/08/18 GCC: (GNU) 2.95.3 20010315 (release)as: Sun WorkShop 6 99/08/18 GCC: (GNU) 2.95.3 20010315 (release)as: Sun WorkShop 6 99/08/18 GCC: (GNU) 2.95.3 20010315 (release)as: S