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The number of instances %d doesn't match. The number of pins %d doesn't match. Error! The number of pins %d doesn't match. Terminal numbers are not match!Error! The number of standard cells doesn't match. Circuit statistics(1): Circuit-Name %s # of modules = %d # of instances = %d # of std cells = %d # of I/O pads = %d # of nets = %d # of pins = %d # of pins per cell = %.2f # of pins per std_cell = %.2f # of fanouts per std_cell = %.2f Max # of pins per cell = %d? Circuit statistics(3): Number of nets with %3d pins = %5d (%4.1f, %4.1f)Bcell %s height doesn't match standard height!Number of rows is %d, should be in (0, %d)White space should be on. Circuit statistics(2): Standard cell height = %d Standard cell total width = %d Average standard cell width = %.1f Number of standard rows = %d Row space = %d White space ratio = %.4f Chip size is %d x %d, Aspect Ratio(W/H) %.2f Global bin %d x %d Average #cells per bin %.2f????zG{?QRset chip size for LEF/DEF format.row %d: width (%d) doesn't match chip width (%d) Standard cell height = %.2f Standard cell total width = %.2f Average standard cell width = %.2f Chip size is %.2f x %.2f, Area %.2f Aspect Ratio(W/H) %.2f?-fParse error in command line..logr.log%dwLog file %s open for write error. ---------------------------------------------# Log file name: %sLog file %s was closed. # Command line: %s # Host : %s# Date : %s.timeaRunning time: %.2f seconds -ldCommand line parse error, around "%s".-it%d-ip-temp-fr-count-yal-tw-pin-tran-kb-bin-cbin-cp-pre-net-bal-mov-chrow-res-si-sg-sm-mul-loc-pad-fmt-cr-qua-sp-dis-ry-ti-nr-hm-gr-row-cpl-cpo-cy-co-con-dl-rd-chp-book%s.aux-wb-wbp-wop-spt-fast-ws%fWhite space should be less than 0.20-rsRow space ratio should be in (0.0, 1.0)-crs-fp-gd-pd-pd shouldn't be zero.-at-at should be a positive integer.-ap-au-aub-hu-rb-hr-hr shouldn't be zero.-ca-ra-ci-ex-cc-ce-tmp-do-nl-pt-pc-pi-dc-ln-ga1-ga2Unknown option "%s"?ə?Can't determine the cell %d, %s 's model(%s) number.Sorting cells by name......doneDUMMY_INPUT Net(%d): %d %s/%sSTANDARDCOREPADPARENTFEEDFEEDTHROUGHunkown type %s in line %dUnknown type %dIOBFPIPOPBINPUTOUTPUTUnkown pin type %dTOPBOTTOMLEFTRIGHT Allocate %dK memory for pins of modulesmalloc error Allocate %dK memory for pin delays of modules MPIN converter out of range. Re-allocate %dK memory for %dth block of pins of modules MDELAY converter out of range. Re-allocate %dK memory for %dth block of delays of modules Error! Pin [%s] can't be found in cell %s, model %s Pin [%s] can't be found in cell %d, model %d line %d: Pin [%s] can't be found in cell %d, model %d Generating interconnecting nets...... number of nets exceed circuit.net_numNumber of Net lists out of range. Generated %d nets so far......Move nets error! Generate %d nets. number of nets %d dosent's match..netWrite netlist file %s......wOpen file error %sNet %s %d : %d done.Read netlist file %s......rCouldn't find file %s%sNetNet %s %d%s:%u: failed assertion net.c%dNumber of net %d is not expected.doneRead %d nets and %d pins from file.There are %d large nets (number of pins >= 50)Coudn't find pin's fanin!Reset all the pins to center-of-cells.Restore all pin locations.Center Pin WL = %.0fcell %d pin %d (%d,%d)Create %s as the bin wirelength report.file %s open for write error!net %d %s xmin=%d xmax=%d ymin=%d ymax=%d bb=%d ?7) @.parrfile open error %sGENR*numrows:%d.gdpN_SC_ROWSRead number of rows = %d from file %s[Mem] Allocate %dK memory for standard rowsmalloc error Sort cells for each row ......doneRow %d length = %d %.2f%%Maximum row length = %d %.2f%%?cell %s (%d) is not in row center.@Y@YInput format is TimberWolf's format. .statrfile %s open error%snum_stdcellsnum_stdcells:%dnum_instancesnum_instances:%dnum_padsnum_pads:%dnum_netsnum_nets:%dnum_pinsnum_pins:%dnum_modelsnum_models:%d Circuit information: #instances = %d #standard cells = %d #IO pads = %d #nets = %d #pins = %d #models = %d Allocate memory for placer: Allocate %dK memory for modelsmalloc error Allocate %dK memory for cells Allocate %dK memory for pins Allocate %dK memory for netsReading Models.......libLibrary file open error. LIBRARY/*ENDLIBRARYMODEL%s%s%s%sENDMODELThe number of models is out of range. BOUNDARYPINPORTDELAYRead %d models%f%f%s%s%sSyntax error in %dLAYERLAYER %dCAPACITANCECAPACITANCE %fRESISTANCERESISTANCE %fSyntax error in line %d.RISETIME=%fFALLTIMEReading Cells.......cktCircuit file open error. CIRCUITENDCIRCUITINSTANCEThe number of cells is out of range. %s%s%s%s%sDELAY=Syntax error in line %d, no delay information%fDELAY=%fBPin name (%s) too long!number of pins out of range.number of pins %d is out of range.number of pins out of range. %s%smalloc error Input format is YAL. .yal.ctlrfile %s open error %sYALCONTROLENDYALCONTROLSyntax error in %sNMODULESNMODULES %dNTERMINALSNTERMINALS %dNCELLSNCELLS %dNPINSNPINS %dNNETSNNETS %dPADDUMMYPADDUMMY %d %dFILESCircuit information from %s: #models = %d #instances = %d #nets = %d #pins = %d Allocate memory for placer: Allocate %dK memory for models Allocate %dK memory for cells Allocate %dK memory for pins Allocate %dK memory for nets Reading %s......In file %s line %d, line is too long.MODULEENDMODULETYPEDIMENSIONSWIDTHSyntax error in line %dWIDTH %fHEIGHTHEIGHT %fIOLISTENDIOLISTNETWORKENDNETWORKSyntax error in file %s line %ddone/**/ Syntax error in line %d%s%s Model name is too long in line %d Unknown type of module in line %dDIMENSIONS %f%f%f%f%f%f%f%f%s%s%s%s%s%s%f%d%s%s%s%f%f%d%snumber of cells %d is beyond control.ICNCnumber of pins %d is beyond control.rPlacement file(%s) open error.Reading Placement file %s ......%s%s%d%f%f%f%f%d%d Cell %s not found when read placement.done ??wPlacement file open error. Create %s file as result......%s %s 0 %.2f %.2f %.2f %.2f %d %d %s %s 0 %.0f %.0f %.0f %.0f %d %d done..dispDisplay file %s open error.Created file %s for display......COLOR WHITE SRD %d %d %d %d SRF %d %d %d %d COLOR BLACK SR %d %d %d %d COLOR GREEN malloc error COLOR GREY SL %d %d %d %d Display mode is not correct!COLOR RED STR %d %d Number of standard cells = %d, Pads = %d STR %d %d AREA = %d x %d STR %d %d Total WL = %.1f @@?.moveMovement Display file(%s) open error.Created file %s for display. SC %d %d 1 @@.nlstCreated file %s for net info......net%5d:%s xspan:%d yspan:%d length:%d numpin:%d done.pthRead file %s for net info......%snet%s%s%s%s%s%s:%u: failed assertion fileio.c%dNet %d not found.Net %d mismatch: bb=%d, length=%dBegin reading I/O pads locations.......padError Pad file. Cell name not found:. ??.rteRouting file %s open for write.Create %s file as routing input file for Labyrinth ......grid %d %d vertical capacity %d horizontal capacity %d num net %d %s %d %d %d %d Input format: LEF/DEF. open file %s to %srreadwriteOpen file error: %s%sdefNamedefName %slefNamelefName %ssdfNamesdfName %sPre read LEF file: MACRO%s%sPINENDpre-read %d models and %d model-pins[Mem] Allocate %dK memory for modelsmalloc error Read LEF file: CLASSSIZE%s%f%s%fread %d models and %d model-pins (without VDD/VSS)?VSSVDDDIRECTIONmodel %s: pin %s: direction unknown!RECT%s%f%f%f%f?model %s's height (%d) is not standard height (%d).check all models --- they have the same height %dDUMMY_INPUTDUMMY_PINDUMMY_OUTPUTafter creating two dummy models: #models = %d, #model-pins = %dRead DEF file: set number of rows to be maximum (%d).DESIGNUNITSDIEAREAROWCOMPONENTS%s%d[Mem] Allocate %dK memory for cellsNETS[Mem] Allocate %dK memory for nets[Mem] Allocate %dK memory for pinsPINS%d pads, out of guess (%d)read %d cells.Expect %d cells, read %d cellsread %d nets.Expect %d nets, read %d netsExpect %d pins, read %d pins.read %d pads (PINS)Expect %d pads, read %d pads.-%s%s%s%dDISTANCEMICRONSUNITS line syntex error.%s%s%d%d%s%s%d%d%sread die size %d x %d%s%s%s%d%d%s%s%d%s%d%s%d%dread more than %d rows.Check %d rows:reverse all the rows to get increasing y coords.row 0: origin is not 0.row %d: origin is not 0.row %d: width doesn't match.row %d: rows are not regular (standard cell height).row %d: row space doesn't match.rows are correct.Chip area %d x %d%s%s%sPLACED Syntax error in line %d: expect PLACED. Syntax error in line %d: expect '('.%d Syntax error in line %d: expect ')'.NFN Syntax error in line %d: expect N or FN. Syntax error in line %d: before ';'line %d: cell %s couldn't be found.Syntax error in line %d: expect '+'.NETOUTPUTINPUTSyntex error in line %d: expect INPUT/OUTPUTUSELAYERSyntax error in line %d, expect '('Syntax error in line %d, expect ')'Syntex error in %d.Syntax error in line %d, before ';'Unknown Pad direction '%c'Unknown Pad direction '%d'Read %d nets and %d pins from file.There are %d large nets (number of pins >= 50)Pre-read SDF file:(IOPATH pre-read %d IOPATHs.Read SDF file: (DIVIDER(CELL(CELLTYPE(INSTANCE(INSTANCE)line %d: expect ')' after %s|line %d: cell %s not found.read %d delays (IOPATHs).[Mem] Allocate %dK memory for cell delay%s%s%s%s%s%sline %d: expecte ')' after %s()line %d: expect '(' around %sline %d: expect a float after '('(%flink all delays (IOPATHs) to cells...cell %s doesn't have delays.okaycell %s model %s: ni=%d no=%d delay_num=%d --- WARNING!Output GCF file ....gcfw gnd!vdd!(ARRIVAL (posedge "CLK") 0.000 11.000 0.000 11.000(DEPARTURE (posedge "CLK") 10.000 10.000 -0.800 -0.800 %s) Output Placed DEF file ...-dragon.defEND COMPONENTScell %s not found.cell %s direction unkown.- %s %s + PLACED ( %d %d ) %s ; initialize names buffer.malloc error Impossible, names need so many space(1G)![Mem] All names occupied %dK bytes. fatal: [%s:%s, line %d]fatalmisc.c Program exit abnormally. panic: panicwarning: warninfoinfo1log2() only works for positive power of two values0s%ldD %ldh %ldm %lds Delete large cells (>=100x minimum)...malloc error Minimum cell width: %d Delete %d cells with width %d.ckt.newwFile open error %sWrite %s file.../* Generated automatically, after deleting large cells from newibm */ CIRCUIT %s INSTANCE %s %s cell %d pinnum = %d(%s %s) ENDCIRCUIT .yal.part%s:%u: failed assertion tran.c %s %s %s ; Delete large cells (>=%dx minimum) and models...Altogether delete %d(%d) cells.yal.new.yalr%sNETWORKENDNETWORKMODULE%s%sENDMODULEdoneCouldn't find cell named %sCouldn't find model named %s.myalfile %s open error Create %s file......MODULE %s; TYPE %s; WIDTH %d; HEIGHT %d; IOLIST; %s %c TOP %d 0 METAL2; ENDIOLIST; ENDMODULE; .pyalPrint module information for .yal file TYPE %s; WIDTH %f; HEIGHT %f; IOLIST; %s %c %.1f %.1f 3 POLY ; ENDIOLIST; ? Create YAL format files..... Identify dangle nets and dangle cells....yal.ctl.new.yal.ctlYALCONTROLS; NMODULES %d; NTERMINALS %d; NCELLS %d; NPINS %d; NNETS %d; FILES %s; ENDYALCONTROLS; done./* Automatically generated by Xiaojian Yang */ FEEDTHROUGH p%d %s %.1f %.1f 3 POLY ; TYPE PARENT; IOLIST; ENDIOLIST; NETWORK; %s %s %s ENDNETWORK; ENDMODULE; ?BB_FLAMEPrint module with pin location information file %s %s %s %.1f %.1f 3 POLY ; ?Error! net %s has 0 pin.There are %d neighber nets for net %dchoose two cells between (%d, %d)Coudn't file a pair.Switched %d pairs of cells.Switch cell %d(net %d) <---> %d(net %d)..gdifCreate %s as the routing input file......(gdif (gdifVersion 1 0 0) (comment "Automatically generated by Dragon") (cell:%s INOUTPin type is not in/out for mode %s, assume it's IN (port:%s (layer MET2) (type %3s) (pt 0 0 )) ) (cell:top (comment "parent module") (instance:%s (cellRef %s) (pt %d %d )) (net:%s (portRef %s (instRef %s)) ) ) ) @q@@.lefopen file %s to %sreadwriteOpen file error: %sCreate %s as the LEF file......NAMESCASESENSITIVE ON ; UNITS DATABASE MICRONS %d ; END UNITS LAYER poly TYPE MASTERSLICE ; END poly LAYER cont TYPE CUT ; END cont LAYER metal1 TYPE ROUTING ; PITCH 1.7 ; WIDTH .8 ; SPACING .6 ; DIRECTION HORIZONTAL ; END metal1 LAYER via1 TYPE CUT ; END via1 LAYER metal2 TYPE ROUTING ; PITCH 2 ; WIDTH .8 ; SPACING .9 ; DIRECTION VERTICAL ; END metal2 LAYER via2 TYPE CUT ; END via2 LAYER metal3 TYPE ROUTING ; PITCH 1.7 ; DIRECTION HORIZONTAL ; END metal3 LAYER OVERLAP TYPE OVERLAP ; END OVERLAP VIA cont DEFAULT LAYER poly ; RECT -.6 -.6 .6 .6 ; LAYER cont ; RECT -.3 -.3 .3 .3 ; LAYER metal1 ; RECT -.4 -.4 .4 .4 ; END cont VIA via1 DEFAULT LAYER metal1 ; RECT -.7 -.7 .7 .7 ; LAYER via1 ; RECT -.3 -.3 .3 .3 ; LAYER metal2 ; RECT -.4 -.4 .4 .4 ; END via1 VIA via2 DEFAULT LAYER metal2 ; RECT -.65 -.65 .65 .65 ; LAYER via2 ; RECT -.3 -.3 .3 .3 ; LAYER metal3 ; RECT -.4 -.4 .4 .4 ; END via2 SPACING SAMENET metal1 metal1 .6 ; SAMENET metal2 metal2 .9 ; SAMENET metal3 metal3 .9 ; SAMENET cont cont .8 ; SAMENET cont via1 .65 ; SAMENET via1 via1 1 ; SAMENET via1 via2 .6 ; SAMENET via2 via1 1 ; END SPACING SITE core SIZE 0.01 BY 0.64 ; CLASS CORE ; SYMMETRY X ; END core MACRO %s CLASS CORE ; SIZE %.2f BY %.2f ; ORIGIN 0 0 ; SYMMETRY X ; SITE core 0 0 N DO 1 BY 1 STEP 0 0 ; PIN P%d DIRECTION INOUT ; USE SIGNAL ; PORT LAYER metal1 ; RECT %.4f %.4f %.4f %.4f ; END END P%d END %s END LIBRARY delete %d empty macros (0 pin).BH?'.defCreate %s as the DEF file......DESIGN %s ; UNITS DISTANCE MICRONS %d ; DIEAREA ( %d %d ) ( %d %d ) ; TRACKS Y 0 DO 1 STEP 100 LAYER metal1 metal2 metal3 ; TRACKS Y 85 DO 472 STEP 170 LAYER metal2 metal3 ; TRACKS Y 85 DO 472 STEP 170 LAYER metal1 metal2 ; TRACKS X 100 DO 802 STEP 200 LAYER metal1 metal2 metal3 ; TRACKS X 0 DO 1 STEP 100 LAYER metal1 metal2 metal3 ; GCELLGRID Y 0 DO 55 STEP 1500 ; GCELLGRID X 0 DO 55 STEP 3000 ; VIAS 3 ; - cont + RECT metal1 ( -40 -40 ) ( 40 40 ) + RECT cont ( -30 -30 ) ( 30 30 ) + RECT poly ( -60 -60 ) ( 60 60 ) ; - via1 + RECT metal2 ( -40 -40 ) ( 40 40 ) + RECT via1 ( -30 -30 ) ( 30 30 ) + RECT metal1 ( -70 -70 ) ( 70 70 ) ; - via2 + RECT metal3 ( -40 -40 ) ( 40 40 ) + RECT via2 ( -30 -30 ) ( 30 30 ) + RECT metal2 ( -65 -65 ) ( 65 65 ) ; END VIAS END DESIGN delete %d dangle cells.COMPONENTS %d ; - %s %s ; END COMPONENTS PINS %d ; - %s + net %s + PLACED ( %d %d ) %c ; END PINS NETS %d ; - %s ( %s P%d ) ; END NETS Assign I/O pad locations...done.Pad width are not identical!!!!!!!!!!!!!!!!!!!!!!!Check pad width finished.pad.%s.pl1wFile open error %s Create %s as pad location file......%s %s 0 %d %d %d %d %d %d Number of rows is invalid....gdpGDP file open error %sCreate %s as gdp file......N_SC_ROWS: %d N_BIN_ROWS: 16 N_BIN_COLS: 16 malloc error Adjust right side I/O pads locations... Maximum row length is %d, +%.1f%%@Y.con.newfile %s open error Write %s as pad/timing constraints file.Pad %s row number incorrect.PAD %s RESTRICT SIDE %c SIDESPACE %8.3f PATHCONSTRAINT %s/%s %s/%s (999) pad..pl1Write %s as pad location file for Dragon.Input format: GSRC bookshelf. .aux.out.auxOptions error, shouldn't read aux file.rfile %s open error %sRowBasedPlacementSyntax error in %s, expecting RowBasedPlacement.Syntax error in %s, expecting ':'.Syntax error in %s:%s, no extension file name.nodes.nets.wts.scl.plSyntax error in %s:%s, file extension name invalidReading %s......UCLANumNodes Allocate %dK memory for cellsmalloc error NumTerminalsNumber of nodes wasn't specified.%s%f%f%sterminalNumber of nodes %d doesn't match.Number of I/O pads %d doesn't match.Finish reading nodes file.NumNets Allocate %dK memory for netsNumPins Allocate %dK memory for pinsNetDegree%s%s%s%snet%.5d%s%s%s%f%f:cell %s couldn't be found.pin%.6dread net file done.Number of net %d is not expected.Number of net %d is not expected, out of rangeNumber of pin %d is not expected.Number of pin %d is not expected, out of rangeRead %d nets and %d pins from file.There are %d large nets (number of pins >= 50)?Right now we don't need to read weights file %sReading layout file %s ......NumrowsCoreRowNumber of rows %d out of range.CoordinateHeightSubrowOrigin%s%s%s%s%s%s%dNumsitesSyntax error in line %dFinish reading layout file.Number of rows read %d is not matching.Row %d width %d is not consistant.Row %d height %d is not consistant.Row %d space is not consistant.Row %d start(SubrowOrigin) %d is not consistant.Reading placement file: %s%s%f%fFinish reading placement file.?Pad %s row number error%s is not a placement file name(.pl)_Dragon.plwWrite bookshelf format Place file %s......pl%%8s%%12%s%%12%s : N done.%dfNeed bookshelf format to change row spacing.There's no need to change row spacing..newSorting pins by cell number ......done. Allocate %dK memory for models Allocate %dK memory for pins of modules Allocate %dK memory for pin delays of modules mod%dSyntax error in line %d, expecting ':'Syntax error in line %d, expecting a number.Set chip dimensions......Number of rows is %d, should be in (0, %d)cell %s height doesn't match standard height!cell standard height %d doesn't match row standard height %d! Circuit statistics(0): Standard cell height = %d Standard cell total width = %d Average standard cell width = %.1f Row space = %d Chip size is %d x %d Aspect Ratio (W/H) %.2f Chip width (with white space) is %d White space is %.2f%c Global bin %d x %d@Y.whiteRead white space file %s......%fWrite white space file %s......%.2fOutput format: GSRC bookshelf. Write bookshelf format auxilary file %s......%s_DG_R%d_WS02RowBasedPlacement : %s.nodes %s.nets %s.wts %s.pl %s.scl %s.nodes%s.nets%s.wts%s.pl%s.sclDoneWrite bookshelf format file %s......nodes NumNodes : %d NumTerminals : %d %s %.1f %.1f terminal wts %s %d nets NumNets : %d NumPins : %d NetDegree : %d %s %2s : 0.5 0.5 scl NumRows : %d No white space setup! Set white space 0CoreRow Horizontal Coordinate : %d Height : %d Sitewidth : %d Sitespacing : %d Siteorient : %d Sitesymmetry : %d SubrowOrigin : %d NumSites : %d End ?wrong parameter for RelativeCoordinatesAdjust().# Created : # User : # Platform : UCLA %s 1.0 %s%s Error in time() xjyang.cs.ucla.eduER Lab, UCLA%s@%s (%s) %s %s %s %s %s ?%s:%u: failed assertion timing.cwhat happened?Calculate wire delays for all net segments...Duplicated source pins in one net (%s)No source pin for net %sdone.node_134671node_1346761Alongest path from p1->p2: %.2f.conopen file %s to %srreadwriteOpen file error: %smalloc error Allocate %dK memory for timing constraint pathsPATHCONSTRAINTPATHCONSTRAINT %s %s (%f)Syntex error in .con file.cell name not found (%s).Read %d timing constraints. extract pin name error (%s)Longest path from %s to %s (%d pins): %s --> %s: delay = %.2ftotal gate delay = %.2f, net delay = %.2f net %s len %d gate-delay = %.2f, net-delay = %.2f, total-delay = %.2f Violation = %.2fTotal timing violation = %.2fcdelay %d delay <=0ARGHHH!out(8)finding the longest path from %s:%sMaximum longest path has a delay of %.2fnsthere is no path from %s to any primary outputlongest path from %s is to %s: %.2fnsFinish assigning weights, max=%d min=%d.DFS traverse pin graph...Allocate %dK memory for pin-edgesmalloc error Re-allocate %dK memory for pin-edgesAllocate %dK memory for net path-edges%d Usage: dp design_name -option dp Detail placer begins working... .pl1.new.pl1After read placement file wirelength = %.0fInitial total wirelength = %.0fAfter reach balance wl = %.0fAfter re-arrange pads total wl = %.0fAfter annealing total wl = %.0fAfter final refinement total wl = %.0fWL improvement = %.2f%cAfter using multi_ports total wl = %.0fDetail placer terminated. Running time: %.2f seconds @YAfter resolve overlap total wl = %.0f%s:%u: failed assertion dpfun.cError cell %d is in row %d, should be in row %dAfter local improvement: WL = %.0fIter%2d: switch try %5d accept %4d shift try%4d accept%2d wl = %.0fBegin flipping only......wl=%.0f Iter %d: flip %d, wl = %.0fAdjust row balance...malloc error .whiter%s file not found, assume white space = 1%%%f %5d moves, wl=%.0f, balance=%4.2fFor balance altogether %d moves were accepted@Y.cellWrite cell width to file %s......wOpen file error %ssort %5d, cell %5d, name %10s model %10d, width=%6d doneNet has %d pins = %dCheck cell row number...Cell %d row=%d, but it is in row %dRow %d contains no cell, invalid for DPRow checking passed.Need specify -bin M N#rows=%d, N=%d, Not match, no pre-processAfter first spread Wirelength = %.0fAfter second spread Wirelength = %.0fAverage number of cells per bin = %.2fMaximum number of cells per bin = %dMinimum number of cells per bin = %dafter bin center: wl = %.f altogether %d large bins cannot be permutated.Too big num %dbin (%d,%d) contains no cell!only %d cells are reconsidered in pre process (should be %d)total %d cells were changed x, (nStd=%d)?Total cell movement = %8.0fAverage movement per cell = %8.0fAverage width per cell = %8dPad %d has more than one pin.Pad %d contains more than one(%d) pin!!!there are %d pure nets out of %d (%.2f%c)There are %d long netsLongest length is %dNet %d reduce from %d to %d, wl=%.0f%2d: acc %4d long %d wl=%.0fTo reduce %d longest net by %d%c, %d tried and %d acceptedWilrelength increase %.6f%c@@?@YThis net %d cannot be reducedplace.scriptNRow = %d, cannot use automatical script generator.Write place.script file......#!/bin/sh CIRCUIT=%s NROW=%d QUAL=%d BASEDIR=/homes/xjyang BINDIR=${BASEDIR}/bin PAD=${BINDIR}/pad GP=${BINDIR}/gp0.2b DP=${BINDIR}/dp ATT0=`expr $QUAL \* 1` ATT1=`expr $QUAL \* 2` ATT2=`expr $QUAL \* 3` ATT3=`expr $QUAL \* 6` TEMP=100 AP=30 FROZEN=5 echo "---`uname -n` $CIRCUIT GP ---" >>$CIRCUIT.time if [ -r pad.$CIRCUIT.pl1 ] then echo "N_SC_ROWS: $NROW" > $CIRCUIT.gdp else echo "Generating I/O Pad locations......" $PAD $CIRCUIT -yal -cpo -row $NROW fi echo "Begin global placement......" echo "Begin detail placement......" $DP $CIRCUIT -yal -res -loc -temp 30 -count 5 -cr 10 -dis -row $NROW done.$GP $CIRCUIT -PAR READ -PAD PL1 pad.$CIRCUIT -o PL1 $CIRCUIT -wl -ub 1 -hmwgts -frozen $FROZEN -ap $AP -noroute%s%s-ip pl1 -hmetis -split %d -bin -b mn %d %d -temp $TEMP -att $ATT%d -pp 3 %s Should use -cbin argument!after snap: WL = %.f N-WL = %dafter permutation process: WL = %.f N-WL = %dNormalized WL = %d?@È?陙BLACKREDBLUEGREENYELLOWCYANGREYalleviateestimatepathmgryan1Success! .congrfile %s open error Read congested file %s......Output for vEdges:%dOutput for hEdges:vThresholdmaxVCongestioncongested string read error.= %dhThresholdmaxHCongestiondone..cmapRead Ryan's congestion map file %s......%d%dbin grid from cmap file doesn't match -bin!V-Cong: Min=%d, Max=%d, Ave=%.1f, Ttl=%dH-Cong: Min=%d, Max=%d, Ave=%.1f, Ttl=%d VC HC---------- %2d %2d V-Cap = %d, H-Cap = %d V-OF = %d, H-OF = %d, Total OF = %d@?@S33Identify congested bins......Calculate bin congested ......Bin congestion max %.3f min %.3f?.disprwDisplay file %s open error.Created file %s for congestion map display......COLOR WHITE SRD %d %d %d %d SRF %d %d %d %d COLOR BLACK SR %d %d %d %d COLOR GREY SL %d %d %d %d STL %d %d (%d,%d) COLOR RED @@?.dispcCOLOR %s < %.1f > %.1f %.1f - %.1f STR %d %d %s @@?.cunitfile %s open error.%f%fRead unit congestion %.1f and %.1f to file %s%f %fWrite unit congestion %.1f and %.1f to file %smalloc error .grFile %s was opened for reading routed path...... file contains %d lines Allocate %dK memory for routed path.Reading path file....nnnn %sNet name %s unkown!This is not enough!hehe %d %dveve %d %dWierd line in the file: %sRouting memory out of range! Total edges %d, horizontal %d, vertical %d Net %s unrouted.Altogether %d unrouted nets.Analyzing routed wirelength.... Total bounding box wirelength = %d, routed wirelength = %d %4d %2d-terminal net: in_bb max %.3f min %.3f avg %.3fplot1%.4f %.4f wierd. %4d good nets with average congestion %.3f %4d bad nets with average congestion %.3f==== Two-terminal nets classified ==== ==== congested threshold = %.2f ==== Type %d: count %d avg=%.3f?@Yuse -tmp x to represent congestion thresh hold.weird.@Y?zG{?????1?*?nulldonecplex.solCPLEX solution file (%s) open error!NAMEENDDATASECTION 2 %c%d%s%s%f%s%dcplex solution file error 1!solution_collecta%f ?Expansion Plan: area %2d: (%2d,%2d)-(%2d,%2d) + %d/%dColumn adjustment at global bin %d x %d. before column adjustment: WL = %.0fmalloc error after column adjustment: WL = %.0fMove %d cells from (%d,%d) ---> (%d,%d) Move cells out of (%d,%d)gain%d Move Net(%d): c(%d) WL = %.0f ---row adjust--- wirelength = %.0f GREEDY: %d %d %d %.f@Y?@Y?Bin dimention (m, n) should be positive integers.malloc error Allocate %dK memory for %d global binsCouldn't assign a number of row for bin. Check -bin m n!?Re-Snap cells into bins......cell %d[%s] is not in chip area. bin grid = (%d, %d), set to (%d, %d) doneSnap cells into bins while keeping their old sequence in row... %d, ===================================== CELL DISTRIBUTION %d x %d -%5d %d after accept %d: wl = %.0f ?Before greedy improve wl = %.0f Iteration %d wl = %.0f?Before single cell greedy improve wl = %.0f?Before single cell greedy improve wwl = %.0f Iteration %d wwl = %.0faccept !After single cell greedy improve wwl = %.0f??There are %d cells to be moved?Bin external nets: Total = %d, Max = %d, Average = %.2fCache memory exceeds maximum number! %dM > %dMAllocated %dK memory for bin external listBin external net-list: Real: total = %d max = %d average=%.1fAdjust bin grid according number of rows: %d x %d ==> %d x %d No need to adjust bin according to number of rows. They are the same. After first adjustment: wirelength = %.0f %d x %d Row width distribution %.4f --- %.4f %d x %d Bin width distribution %.4f --- %.4f %d x %d Bin c_num distribution %6d --- %6d Hey, N is too small!check if all the standard cells were placed... NO! cell %s hasn't been placed yet! YES!check if there's overlap...NIL OVERLAP at row %d between cell %s and cell %s too many overlaps. stop checking. No overlap.check if there's row overflow... row %d overflow: row width %d, max cell right bound %d. No row overflow. together %d row(s) has(have) overflow.check if all cells are in the rows... cell %s is supposed to be in row %d but not. too many violations, stop checking. Good, all cells are in the rows.check if all cells are abut... Cells are not abut between %s and %s. Too many cell abut violations, stop checking. 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