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J9Ή|ϋJE9]|e[^_]É'UJWVS19}eJ=M v19}L1ɍFD DDDJ9|ċJC9|[^_]Ít&UtJUM R$ $$ʃJ JJJxJJ ]Ðt&UW1VSJ9JEM E1;MW]$1t& J}EE mE]mE2QA$ J}EE mE]mED2ƠJE9|؋JG9d؃[^_]Ív'UU1M x;J}x ; J}]ÍUU1M ;U|;U;M| ;M]Ív'UW}VuStxM ME D O19}#= M &DC9ˉDd| < M LdMM tr M D>9D EPDPh E} tc M 4\\t5L릍Et!Mte[^_]à h@ E$E;`JCȐ hc E맍&D>9D8Mp'UWVS(EhE EE;`JE LM}49 M   T 4‹D )ЍW9~2ET < R|Whi E} t} M u T4<tt\zEt%]t e[^_]Ít& h EE$E;`JÍ h@ E띍&UWVS,`JEEE9EEEE M EЉEԡLE̋E̋}ԋ0 |\]Љ]܍v' D\ T4L‹D4)щЋT);MME;M~nMEM܍p>rrandom.seed%dwp>@Y@ Global placement running time %.2fs, Detailed placement %.2fs Partition %.2fs, bin-annealing %.2fs, cell-annealing %.2fs%s %s %s %s Unknown input format!The number of modules %d doesn't match. The number of instances %d doesn't match. The number of pins %d doesn't match. Terminal numbers are not match! Circuit statistics(1): Circuit-Name %s # of modules = %d # of instances = %d # of std cells = %d # of I/O pads = %d # of nets = %d # of pins = %d # of pins per cell = %.2f # of pins per std_cell = %.2f # of fanouts per std_cell = %.2f Max # of pins per cell = %dError! The number of standard cells doesn't match. Error! The number of pins %d doesn't match. Error! The number of instances %d doesn't match. Error! The number of modules %d doesn't match. Circuit statistics(3): Number of nets with %3d pins = %5d (%4.1f, %4.1f)Bcell %s height doesn't match standard height!Number of rows is %d, should be in (0, %d) Circuit statistics(2): Standard cell height = %d Standard cell total width = %d Average standard cell width = %.1f Number of standard rows = %d Row space = %d White space ratio = %.4f Chip size is %d x %d, Aspect Ratio(W/H) %.2f Global bin %d x %d Average #cells per bin %.2fWhite space should be on.??{Gz?RQ?set chip size for LEF/DEF format.Number of rows is %d, should be in (1, %d)row %d: width (%d) doesn't match chip width (%d) Standard cell height = %.2f Standard cell total width = %.2f Average standard cell width = %.2f Chip size is %.2f x %.2f, Area %.2f Aspect Ratio(W/H) %.2f?Parse error in command line.Command line parse error, around "%s".-temp-count-yal-pin-tran-bin-cbin-pre-net-bal-mov-chrow-res-mul-loc-pad-fmt-qua-dis-row-cpl-cpo-con-chp-book-wbp-wop-spt-fast-crs-aub-tmp-ga1-ga2Unknown option "%s"%d%f-hr shouldn't be zero.-at should be a positive integer.-pd shouldn't be zero.Row space ratio should be in (0.0, 1.0)White space should be less than 0.20%s.aux?.logr.log%dw---------------------------------------------# Log file name: %sLog file %s open for write error. Log file %s was closed. # Command line: %s # Host : %s# Date : %s.timeaRunning time: %.2f seconds Can't determine the cell %d, %s 's model(%s) number.0PqSorting cells by name......doneDUMMY_INPUTlargest cell width %d, smallest cell width %d. Net(%d): %d %s/%sSTANDARDCOREPADPARENTFEEDFEEDTHROUGHunkown type %s in line %dPIPOPBINPUTOUTPUTIOBF Allocate %dK memory for pins of modules Allocate %dK memory for pin delays of modules malloc error MPIN converter out of range.Error! Pin [%s] can't be found in cell %s, model %s line %d: Pin [%s] can't be found in cell %d, model %d Unknown type %dUnkown pin type %dTOPBOTTOMLEFTRIGHT Re-allocate %dK memory for %dth block of pins of modules MDELAY converter out of range. Re-allocate %dK memory for %dth block of delays of modules Pin [%s] can't be found in cell %d, model %d Generating interconnecting nets...... Move nets error! Generate %d nets. number of nets %d dosent's match..netWrite netlist file %s......wNet %s %d : %d done.Open file error %snumber of nets exceed circuit.net_numNumber of Net lists out of range. Generated %d nets so far......Read netlist file %s......r%s%dNet %s %dNumber of net %d is not expected.doneRead %d nets and %d pins from file.There are %d large nets (number of pins >= 50)Couldn't find file %snet.c%s:%u: failed assertion Reset all the pins to center-of-cells.Center Pin WL = %.0fRestore all pin locations.Coudn't find pin's fanin!Create %s as the bin wirelength report.net %d %s xmin=%d xmax=%d ymin=%d ymax=%d bb=%d file %s open for write error! )7?@cell %d pin %d (%d,%d).parrGENR*numrows:%dfile open error %s.gdpN_SC_ROWSRead number of rows = %d from file %sSort cells for each row ......donemalloc error Maximum row length %d %.2f%% chip width, +%.2f%% row widthY@[Mem] Allocate %dK memory for standard rowsRow %d length = %d %.2f%%Y@Input format is TimberWolf's format. .statrnum_stdcells%snum_instancesnum_padsnum_netsnum_pinsnum_modelsnum_models:%dnum_pins:%dnum_nets:%dnum_pads:%dnum_instances:%dnum_stdcells:%d Circuit information: #instances = %d #standard cells = %d #IO pads = %d #nets = %d #pins = %d #models = %d Allocate memory for placer: Allocate %dK memory for models Allocate %dK memory for cells Allocate %dK memory for pins Allocate %dK memory for netsmalloc error file %s open errorReading Models.......libLIBRARYENDLIBRARYMODELENDMODELBOUNDARYPORTDELAYThe number of models is out of range. %s%s%s%sRead %d modelsLibrary file open error. %f%f%s%s%sLAYERLAYER %dCAPACITANCECAPACITANCE %fRESISTANCERESISTANCE %fSyntax error in %dRISETIME=%fFALLTIMESyntax error in line %d.Reading Cells.......cktCIRCUITENDCIRCUITINSTANCEThe number of cells is out of range. %s%s%s%s%sDELAY=Syntax error in line %d, no delay informationDELAY=%f%fCircuit file open error. BPin name (%s) too long!number of pins out of range.number of pins %d is out of range.number of pins out of range. %s%sInput format is YAL. .yal.ctlrYALCONTROL%sENDYALCONTROLNMODULESNTERMINALSNCELLSNPINSNNETSPADDUMMYFILESPADDUMMY %d %dNNETS %dNPINS %dNCELLS %dNTERMINALS %dNMODULES %dSyntax error in %sCircuit information from %s: #models = %d #instances = %d #nets = %d #pins = %d Allocate memory for placer: Allocate %dK memory for models Allocate %dK memory for cells Allocate %dK memory for pins Allocate %dK memory for nets malloc error file %s open error Reading %s......In file %s line %d, line is too long.MODULEENDMODULETYPEDIMENSIONSWIDTHHEIGHTIOLISTENDIOLISTNETWORKENDNETWORKSyntax error in file %s line %dHEIGHT %fSyntax error in line %dWIDTH %fdoneDIMENSIONS %f%f%f%f%f%f%f%f%s%s%s%s%s%s%f%d%s Syntax error in line %d%s%s%f%f%d%s%s%sICNCnumber of pins %d is beyond control.number of cells %d is beyond control. Model name is too long in line %d Unknown type of module in line %drReading Placement file %s ......%s%s%d%f%f%f%f%d%d Cell %s not found when read placement.done Placement file(%s) open error.?wCreate %s file as result......%s %s 0 %.0f %.0f %.0f %.0f %d %d done.%s %s 0 %.2f %.2f %.2f %.2f %d %d Placement file open error. .dispCreated file %s for display......COLOR WHITE SRD %d %d %d %d SRF %d %d %d %d COLOR BLACK SR %d %d %d %d COLOR GREEN Display mode is not correct!COLOR RED SL %d %d %d %d STR %d %d Number of standard cells = %d, Pads = %d STR %d %d AREA = %d x %d STR %d %d Total WL = %.1f COLOR GREY malloc error Display file %s open error.@@?.moveCreated file %s for display. SC %d %d 1 Movement Display file(%s) open error.@@.nlstCreated file %s for net info......net%5d:%s xspan:%d yspan:%d length:%d numpin:%d done.pthRead file %s for net info......net%s%s%s%s%s%s%dNet %d mismatch: bb=%d, length=%dNet %d not found.fileio.c%s:%u: failed assertion Begin reading I/O pads locations.......padError Pad file. Cell name not found:. ?.rteCreate %s file as routing input file for Labyrinth ......grid %d %d vertical capacity %d horizontal capacity %d num net %d %s %d %d %d %d Routing file %s open for write.Input format: LEF/DEF. readopen file %s to %srdefName%slefNamesdfNamesdfName %slefName %sdefName %sOpen file error: %sPre read LEF file: MACROPINEND%s%spre-read %d models and %d model-pins[Mem] Allocate %dK memory for modelsmalloc error Read LEF file: CLASSSIZE%s%f%s%fread %d models and %d model-pins (without VDD/VSS)?DIRECTIONRECT%s%f%f%f%fmodel %s: pin %s: direction unknown!?DUMMY_INPUTDUMMY_PINDUMMY_OUTPUTafter creating two dummy models: #models = %d, #model-pins = %dRead DEF file: set number of rows to be maximum (%d).DESIGNUNITSDIEAREAROWCOMPONENTSNETSPINSExpect %d pads, read %d pads.read %d pads (PINS)Expect %d nets, read %d nets, %d 0-pin netsExpect %d pins, read %d pins.Expect %d nets, read %d netsread %d nets.Expect %d cells, read %d cellsread %d cells.%s%d%d pads, out of guess (%d)[Mem] Allocate %dK memory for nets[Mem] Allocate %dK memory for pins[Mem] Allocate %dK memory for cellsDISTANCE%s%s%s%dUNITS line syntex error.MICRONS%s%s%s%d%d%s%s%d%s%d%s%d%dread more than %d rows.Check %d rows:reverse all the rows to get increasing y coords.row 0: origin is not 0.row %d: origin is not 0.row %d: width doesn't match.row %d: rows are not regular (standard cell height).row %d: row space doesn't match.rows are correct.Chip area %d x %d%s%s%s Syntax error in line %d: before ';'PLACED Syntax error in line %d: expect PLACED. Syntax error in line %d: expect '('.%d Syntax error in line %d: expect ')'. Syntax error in line %d: expect N or FN.op7pp7qUqline %d: cell %s couldn't be found.LAYERSyntax error in line %d, expect '('Syntax error in line %d, expect ')'Syntex error in %d.OUTPUTINPUTSyntex error in line %d: expect INPUT/OUTPUTSyntax error in line %d: expect '+'.uvvv wRead %d nets and %d pins from file.There are %d large nets (number of pins >= 50)Pre-read SDF file:(IOPATH pre-read %d IOPATHs.Read SDF file: (DIVIDER(CELL(CELLTYPE(INSTANCE(INSTANCE)line %d: expect ')' after %sline %d: cell %s not found.read %d delays (IOPATHs).%s%s%s%s%s%sline %d: expect '(' around %s(%fline %d: expect a float after '('line %d: expecte ')' after %slink all delays (IOPATHs) to cells...okaycell %s doesn't have delays.cell %s model %s: ni=%d no=%d delay_num=%d --- WARNING!Output GCF file ....gcfwritewgnd! vdd!(ARRIVAL (posedge "CLK") 0.000 11.000 0.000 11.000 %s) (DEPARTURE (posedge "CLK") 10.000 10.000 -0.800 -0.800Output Placed DEF file ...-dragon.defEND COMPONENTScell %s direction unkown.- %s %s + PLACED ( %d %d ) %s ; cell %s not found.Unknown Pad direction '%d'model %s's height (%d) is not standard height (%d).check all models --- they have the same height %d%s%s%d%d%s%s%d%d%sread die size %d x %dUnknown Pad direction '%c'[Mem] Allocate %dK memory for cell delayinitialize names buffer.malloc error Impossible, names need so many space(1G)![Mem] All names occupied %dK bytes. fatal: misc.cfatal [%s:%s, line %d]Program exit abnormally. panic: panicwarning: warninfoinfo10s%ldD %ldh %ldm %lds log2() only works for positive power of two valuesDelete large cells (>=100x minimum)...Minimum cell width: %d Delete %d cells with width %d.ckt.newwWrite %s file.../* Generated automatically, after deleting large cells from newibm */ CIRCUIT %s ENDCIRCUIT .yal.part %s %s %s ; File open error %s INSTANCE %s %s cell %d pinnum = %d(%s %s) malloc error tran.c%s:%u: failed assertion Delete large cells (>=%dx minimum) and models...Altogether delete %d(%d) cells.yal.new.yalrNETWORK%sENDNETWORKMODULEENDMODULE%s%sdone.myalCreate %s file.......pyalfile %s open error MODULE %s; TYPE %s; WIDTH %d; HEIGHT %d; IOLIST; %s %c TOP %d 0 METAL2; ENDIOLIST; ENDMODULE; Print module information for .yal file TYPE %s; WIDTH %f; HEIGHT %f; IOLIST; %s %c %.1f %.1f 3 POLY ; ENDIOLIST; ? Create YAL format files..... Identify dangle nets and dangle cells....yal.ctl.newYALCONTROLS; NMODULES %d; NTERMINALS %d; NCELLS %d; NPINS %d; NNETS %d; FILES %s; ENDYALCONTROLS; done./* Automatically generated by Xiaojian Yang */ FEED p%d %s %.1f %.1f 3 POLY ; TYPE PARENT; IOLIST; ENDIOLIST; NETWORK; %s %s %s ENDNETWORK; ENDMODULE; THROUGH.yal.ctl?Print module with pin location information file %s %s %s %.1f %.1f 3 POLY ; ?Error! net %s has 0 pin.There are %d neighber nets for net %dchoose two cells between (%d, %d)Switched %d pairs of cells.Coudn't file a pair.Switch cell %d(net %d) <---> %d(net %d)..gdifCreate %s as the routing input file......(gdif (gdifVersion 1 0 0) (comment "Automatically generated by Dragon") (cell:%s Pin type is not in/out for mode %s, assume it's IN (port:%s (layer MET2) (type %3s) (pt 0 0 )) ) (cell:top (comment "parent module") (instance:%s (cellRef %s) (pt %d %d )) (net:%s (portRef %s (instRef %s)) ) ) ) Scaling all cell/model size ...total std width = %dexpected number of rows is %d?+>P@.lefwriteopen file %s to %sCreate %s as the LEF file......VERSION 5.1 ; NAMESCASESENSITIVE ON ; UNITS DATABASE MICRONS %d ; END UNITS LAYER POLY1 TYPE MASTERSLICE ; END POLY1 LAYER METAL1 TYPE ROUTING ; WIDTH 0.23 ; SPACING 0.23 ; SPACING 0.6 RANGE 10.0 100000.0 ; PITCH 0.56 ; DIRECTION HORIZONTAL ; END METAL1 LAYER VIA12 TYPE CUT ; END VIA12 LAYER METAL2 TYPE ROUTING ; WIDTH 0.28 ; SPACING 0.28 ; PITCH 0.66 ; DIRECTION VERTICAL ; END METAL2 LAYER VIA23 TYPE CUT ; END VIA23 LAYER METAL3 TYPE ROUTING ; PITCH 1.12 ; DIRECTION HORIZONTAL ; END METAL3 LAYER VIA34 TYPE CUT ; END VIA34 LAYER METAL4 TYPE ROUTING ; WIDTH 0.44 ; SPACING 0.46 ; PITCH 1.32 ; DIRECTION VERTICAL ; END METAL4 LAYER OVERLAP TYPE OVERLAP ; END OVERLAP VIA via1 DEFAULT LAYER METAL1 ; RECT -0.19 -0.14 0.19 0.14 ; LAYER VIA12 ; RECT -0.13 -0.13 0.13 0.13 ; LAYER METAL2 ; RECT -0.19 -0.14 0.19 0.14 ; END via1 VIA via2 DEFAULT LAYER VIA23 ; RECT -0.13 -0.13 0.13 0.13 ; LAYER METAL3 ; RECT -0.19 -0.14 0.19 0.14 ; END via2 VIA via3 DEFAULT LAYER METAL3 ; RECT -0.24 -0.19 0.24 0.19 ; LAYER VIA34 ; RECT -0.18 -0.18 0.18 0.18 ; LAYER METAL4 ; RECT -0.27 -0.27 0.27 0.27 ; END via3 SPACING SAMENET METAL1 METAL1 0.23 ; SAMENET METAL2 METAL2 0.28 ; SAMENET METAL3 METAL3 0.28 ; SAMENET METAL4 METAL4 0.46 ; SAMENET VIA12 VIA12 0.26 ; SAMENET VIA23 VIA23 0.26 ; SAMENET VIA34 VIA34 0.26 ; END SPACING SITE core SIZE 0.66 BY 5.04 ; CLASS CORE ; SYMMETRY y ; END core MACRO %s CLASS CORE ; SIZE %.2f BY %.2f ; ORIGIN 0.00 0.00 ; SYMMETRY x y ; SITE core ; PIN P%d DIRECTION INOUT ; USE SIGNAL ; PORT LAYER METAL1 ; RECT %.4f %.4f %.4f %.4f ; END END P%d END %s END LIBRARY delete %d empty macros (0 pin).Open file error: %s?BY@.defCreate %s as the DEF file......DESIGN %s ; UNITS DISTANCE MICRONS %d ; END DESIGN delete %d dangle cells.COMPONENTS %d ; - %s %s ; END COMPONENTS NETS %d ; - %s ( %s P%d ) ; END NETS Couldn't find cell named %sCouldn't find model named %sPINS %d ; - %s + net %s ; END PINS Assign I/O pad locations...done.pad.%s.pl1wCreate %s as pad location file......%s %s 0 %d %d %d %d %d %d File open error %s malloc error Adjust right side I/O pads locations... Maximum row length is %d, +%.1f%%Y@.con.newWrite %s as pad/timing constraints file.Pad %s row number incorrect.PAD %s RESTRICT SIDE %c SIDESPACE %8.3f PATHCONSTRAINT %s/%s %s/%s (999) file %s open error pad..pl1Write %s as pad location file for Dragon.Number of rows is invalid....gdpCreate %s as gdp file......N_SC_ROWS: %d N_BIN_ROWS: 16 N_BIN_COLS: 16 GDP file open error %sPad width are not identical!!!!!!!!!!!!!!!!!!!!!!!Check pad width finished..aux.outr%sSyntax error in %s:%s, no extension file name.nodes.nets.wts.sclSyntax error in %s:%s, file extension name invalidSyntax error in %s, expecting ':'.RowBasedPlacementSyntax error in %s, expecting RowBasedPlacement.file %s open error .auxOptions error, shouldn't read aux file.Reading %s......UCLANumNodesNumTerminals%s%s%s%s%fterminalSyntax error at line %d: expect two numbersNumber of nodes wasn't specified. Allocate %dK memory for cellsmalloc error Number of nodes %d doesn't match.Number of I/O pads %d doesn't match.Finish reading nodes file.NumNetsNumPinsNetDegree%s%s%s%f%fpin%.6dcell %s couldn't be found.net%.5dread net file done.Number of net %d is not expected.Number of pin %d is not expected.Read %d nets and %d pins from file.There are %d large nets (number of pins >= 50)Number of pin %d is not expected, out of rangeNumber of net %d is not expected, out of range Allocate %dK memory for pins Allocate %dK memory for nets?Reading layout file %s ......NumrowsCoreRowCoordinateHeightSitewidthSitespacingSubrowOrigin%s%s%s%s%s%s%dNumsitesSyntax error in line %dNumber of rows %d out of range.Finish reading layout file.Number of rows read %d is not matching.Row %d width %d is not consistant.Row %d height %d is not consistant.Row space between row-%d and row-%d is not consistant.Row %d start(SubrowOrigin) %d is not consistant.Reading placement file: %s%s%f%f%s%sFinish reading placement file.?Pad %s row number errorwWrite bookshelf format Place file %s......pl%%8s%%12%s%%12%s : N done%s is not a placement file name(.pl).%df Allocate %dK memory for models Allocate %dK memory for pins of models Allocate %dK memory for pin delays of models mod%dSet chip dimensions......Number of rows is %d, should be in (0, %d)cell %s height doesn't match standard height!cell standard height %d doesn't match row standard height %d! Circuit statistics(0): Standard cell height = %d Standard cell total width = %d Average standard cell width = %.1f Number of standard rows = %d Row space = %d Chip size is %d x %d Aspect Ratio (W/H) %.2f White space %.2f%c Global bin %d x %d?Y@Write bookshelf format auxilary file %s......%s_DG_R%d_WS02RowBasedPlacement : %s.nodes %s.nets %s.wts %s.pl %s.scl %s.nodes%s.nets%s.wts%s.pl%s.sclDoneWrite bookshelf format file %s......nodes NumNodes : %d NumTerminals : %d %s %.1f %.1f terminalnets NumNets : %d NumPins : %d NetDegree : %d %s %2s : 0.5 0.5 scl NumRows : %d CoreRow Horizontal Coordinate : %d Height : %d Sitewidth : %d Sitespacing : %d Siteorient : %d Sitesymmetry : %d SubrowOrigin : %d NumSites : %d End No white space setup! Set white space 0Input format: GSRC bookshelf. Need bookshelf format to change row spacing.There's no need to change row spacing..newOutput format: GSRC bookshelf. .whiteWrite white space file %s......%.2fdone.Sorting pins by cell number ......Right now we don't need to read weights file %sSyntax error in line %d, expecting a number.Syntax error in line %d, expecting ':'Read white space file %s......wts %s %d # Created : # User : # Platform : UCLA %s 1.0 %s%sCalculate wire delays for all net segments...done.No source pin for net %sDuplicated source pins in one net (%s)timing.c%s:%u: failed assertion node_134671node_1346761Alongest path from p1->p2: %.2f.conreadopen file %s to %sr Allocate %dK memory for timing constraint pathsPATHCONSTRAINTPATHCONSTRAINT %s %s (%f)Syntex error in .con file.cell name not found (%s).Read %d timing constraints.malloc error Open file error: %sLongest path from %s to %s (%d pins):what happened? %s --> %s: delay = %.2ftotal gate delay = %.2f, net delay = %.2f gate-delay = %.2f, net-delay = %.2f, total-delay = %.2f Violation = %.2fcdelay %d delay <=0out(8)finding the longest path from %s:%sMaximum longest path has a delay of %.2fnsARGHHH!Finish assigning weights, max=%d min=%d. extract pin name error (%s)Total timing violation = %.2flongest path from %s:%s is to %s:%s ( %.2fns )there is no path from %s to any primary outputDFS traverse pin graph...%d Allocate %dK memory for net path-edgesmalloc error Allocate %dK memory for pin-edges Re-allocate %dK memory for pin-edgesdp Detail placer begins working... After read placement file wirelength = %.0fInitial total wirelength = %.0fAfter reach balance wl = %.0f.pl1.newAfter annealing total wl = %.0fAfter final refinement total wl = %.0fWL improvement = %.2f%cAfter re-arrange pads total wl = %.0fAfter using multi_ports total wl = %.0fDetail placer terminated. Running time: %.2f seconds .pl1Y@dpcheck Copyright (c) 2001-2002 ER Lab, UCLAUsage: dpcheck -f aux_file aux_file: bookshelf format auxilary file name; dpfun.c%s:%u: failed assertion Error cell %d is in row %d, should be in row %dBegin flipping only......wl=%.0f Iter %d: flip %d, wl = %.0fIter%2d: switch try %5d accept %4d shift try%4d accept%2d wl = %.0fAdjust row balance....whiter%fFor balance altogether %d moves were accepted %5d moves, wl=%.0f, balance=%4.2f%s file not found, assume white space = 1%%malloc error Y@.cellWrite cell width to file %s......wsort %5d, cell %5d, name %10s model %10d, width=%6d doneOpen file error %sAverage number of cells per bin = %.2fMaximum number of cells per bin = %dMinimum number of cells per bin = %dafter bin center: wl = %.f altogether %d large bins cannot be permutated.Too big num %donly %d cells are reconsidered in pre process (should be %d)total %d cells were changed x, (nStd=%d)bin (%d,%d) contains no cell!?Total cell movement = %8.0fAverage movement per cell = %8.0fAverage width per cell = %8dPad %d has more than one pin.Pad %d contains more than one(%d) pin!!!there are %d pure nets out of %d (%.2f%c)There are %d long netsLongest length is %dNet %d reduce from %d to %d, wl=%.0fTo reduce %d longest net by %d%c, %d tried and %d acceptedWilrelength increase %.6f%c%2d: acc %4d long %d wl=%.0fAfter resolve overlap total wl = %.0f@@?Y@This net %d cannot be reducedplace.scriptWrite place.script file......#!/bin/sh CIRCUIT=%s NROW=%d QUAL=%d BASEDIR=/homes/xjyang BINDIR=${BASEDIR}/bin PAD=${BINDIR}/pad GP=${BINDIR}/gp0.2b DP=${BINDIR}/dp ATT0=`expr $QUAL \* 1` ATT1=`expr $QUAL \* 2` ATT2=`expr $QUAL \* 3` ATT3=`expr $QUAL \* 6` TEMP=100 AP=30 FROZEN=5 echo "---`uname -n` $CIRCUIT GP ---" >>$CIRCUIT.time if [ -r pad.$CIRCUIT.pl1 ] then echo "N_SC_ROWS: $NROW" > $CIRCUIT.gdp else echo "Generating I/O Pad locations......" $PAD $CIRCUIT -yal -cpo -row $NROW fi echo "Begin global placement......" echo "Begin detail placement......" $DP $CIRCUIT -yal -res -loc -temp 30 -count 5 -cr 10 -dis -row $NROW done.NRow = %d, cannot use automatical script generator.-wl -ub 1 -hmwgts $GP $CIRCUIT -PAR READ -PAD PL1 pad.$CIRCUIT -o PL1 $CIRCUIT %s%s-ip pl1 -hmetis -split %d -bin -b mn %d %d -temp $TEMP -frozen $FROZEN -ap $AP -att $ATT%d -noroute%s -pp 3 after snap: WL = %.f N-WL = %dafter permutation process: WL = %.f N-WL = %dAfter local improvement: WL = %.0fNormalized WL = %dShould use -cbin argument!Net has %d pins = %d#rows=%d, N=%d, Not match, no pre-processAfter first spread Wirelength = %.0fAfter second spread Wirelength = %.0fNeed specify -bin M N?@?Check cell row number...Cell %d row=%d, but it is in row %dRow checking passed.Row %d contains no cell, invalid for DPGREYCYANYELLOWGREENBLUEREDBLACKalleviateestimatepathryan1Success! .congrRead congested file %s......Output for vEdges:Output for hEdges:vThresholdhThresholdmaxHCongestion= %ddone.congested string read error.maxVCongestion%dfile %s open error .cmapRead Ryan's congestion map file %s......%d%dbin grid from cmap file doesn't match -bin!V-Cong: Min=%d, Max=%d, Ave=%.1f, Ttl=%dH-Cong: Min=%d, Max=%d, Ave=%.1f, Ttl=%d V-Cap = %d, H-Cap = %d V-OF = %d, H-OF = %d, Total OF = %d VC HC---------- %2d %2d@?33S@Identify congested bins......Calculate bin congested ......Bin congestion max %.3f min %.3f?.disprwCreated file %s for congestion map display......COLOR WHITE SRD %d %d %d %d SRF %d %d %d %d COLOR BLACK SR %d %d %d %d COLOR GREY SL %d %d %d %d STL %d %d (%d,%d) COLOR RED Display file %s open error.@@?.dispcCOLOR %s %.1f - %.1f STR %d %d %s > %.1f < %.1f @@?.grFile %s was opened for reading routed path...... file contains %d lines Allocate %dK memory for routed path.Reading path file....nnheveWierd line in the file: %sve %d %dhe %d %dnn %sThis is not enough!Net name %s unkown!Routing memory out of range! Total edges %d, horizontal %d, vertical %dAltogether %d unrouted nets. Net %s unrouted.malloc error file %s open error.Analyzing routed wirelength.... Total bounding box wirelength = %d, routed wirelength = %d %4d %2d-terminal net: in_bb max %.3f min %.3f avg %.3fplot1 %4d good nets with average congestion %.3f %4d bad nets with average congestion %.3f==== Two-terminal nets classified ==== ==== congested threshold = %.2f ==== Type %d: count %d avg=%.3f%.4f %.4f wierd.Y@weird.use -tmp x to represent congestion thresh hold.Y@{Gz??congestion cost function??88V-Congestion: Max = %.f, Min = %.f, Avg = %.3fH-Congestion: Max = %.f, Min = %.f, Avg = %.3fV-Cap = %d, H-Cap = %dBin-Congestion: Max = %.f, Min = %.f, Avg = %.fArea-Bin-Congestion: Max = %.f, Min = %.f, Avg = %.fV-Overflow: Global = %.1f, Max = %.f Local = %.1f, Max = %.fH-Overflow: Global = %.1f, Max = %.fAlleviate congestion start.....Model: V-Cap %.1f V-Thresh %.1f, H-Cap %.1f H-Thresh %.1f Current WL=%.fInitital chip congestion = %.2fInitital region congestion = %.2fCurrent congestion = %.2f-----------------------------------After optimization: Current area congestion = %.2fAfter legalization: Final chip congestion = %.2fFinal region congestion = %.2fFinal area congestion = %.2fc=%7.1f Gen%4d Att%4d Acc%4d cong=%6.1f, WL=%.frcong.c%s:%u: failed assertion Identified congested area : (%d,%d) -- (%d,%d)Number of congested areas exceeds range (%d)@@Determine expansion of congested regions by tmp: region %d: expand %d / %dY@?Area %d(%2dx%2d) Allocate %dK memory for congested area expansionSet expansion for each congestion regions: region %d: expand1 %d/%d expand2 %d/%dY@? Area %d: density1=%.2f density2=%.2fexpansion method wrong!\Problem name: %s.lp Minimize cmax Subject to bounds 0 <= x%d <= 1 End File %s was closed as a CPLEX file. binary x%d File %s open for write error.NAMEENDDATA%s%dcplex solution file error 1!SECTION 2 %c%d%s%s%fCPLEX solution file (%s) open error!?Expansion Plan: area %2d: (%2d,%2d)-(%2d,%2d) + %d/%d.cunit%f%fRead unit congestion %.1f and %.1f to file %s%f %fWrite unit congestion %.1f and %.1f to file %sWe have %d congested areas: Area %d: (%2d,%2d) -- (%2d,%2d)c%d_%d: %+7.3fx%d - cmax <= %7.3f %+7.3fx%d %+7.3fx%dCPLEX Optimizing, wait......cplex nulldoneColumn adjustment at global bin %d x %d. before column adjustment: WL = %.0f after column adjustment: WL = %.0fmalloc error Move cells out of (%d,%d)gain%d ---row adjust--- wirelength = %.0f GREEDY: %d %d %d %.fY@Y@Move %d cells from (%d,%d) ---> (%d,%d) Move Net(%d): c(%d) WL = %.0f Allocate %dK memory for %d global binsmalloc error Bin dimention (m, n) should be positive integers.Snap cells into bins......donecell %d[%s] is not in chip area. bin grid = (%d, %d), set to (%d, %d) Re-?Snap cells into bins while keeping their old sequence in row...??===================================== CELL DISTRIBUTION %d x %d %5d -after accept %d: wl = %.0f ?Before greedy improve wl = %.0f Iteration %d wl = %.0f?Before single cell greedy improve wl = %.0f?Before single cell greedy improve wwl = %.0fAfter single cell greedy improve wwl = %.0faccept ! Iteration %d wwl = %.0f??Bin external nets: Total = %d, Max = %d, Average = %.2fCache memory exceeds maximum number! %dM > %dMAllocated %dK memory for bin external listBin external net-list: Real: total = %d max = %d average=%.1fAdjust bin grid according number of rows: %d x %d ==> %d x %d After first adjustment: wirelength = %.0f No need to adjust bin according to number of rows. They are the same.? %d x %d Bin width distribution %.4f --- %.4f %d x %d Bin c_num distribution %6d --- %6d Hey, N is too small!Couldn't assign a number of row for bin. Check -bin m n!? %d x %d Row width distribution %.4f --- %.4f %d, %d There are %d cells to be movedcheck if there's overlap... OVERLAP at row %d between cell %s and cell %s No overlap. too many overlaps. stop checking.check if there's row overflow... row %d overflow: row width %d, max cell right bound %d. total %d rows have overflow. No row overflow.check if all cells are in the rows... cell %s is supposed to be in row %d but not. Good, all cells are in the rows. too many violations, stop checking.check if all cells are abut... Cells are not abut between %s and %s. Good, all cells are abut. Too many cell abut violations, stop checking. Min cell distance %d (%d), Max %d (%d) min boundingbox %d, max bounding box %d.change max to %dwritewire-distopen file %s to %swoutput wirelength distribution for current placement...%d %d done.Open file error: %s2 Check if the current placement is correct...check if all the standard cells were placed... YES! NO! cell %s hasn't been placed yet!0d/**/x>L??33?ff@ff&@333@L@>L???@@333@L@???1?*?N^n~΋ދ.>N^n~Όތ.>N^n~΍ލ#  ,(8  00 ooo>@d4d4,<;e#tIr$IsgVs2k !"#%&1253L4e5}689;=>?)@?AVBnCDEFGHINtQRSTUVX*[D^\btx{~ ! < W t  - G {   #Z 4` < C F S Z ^ lt8yY2 7L8`sbFJ#-`sGJ"KSTZ^a2bj/S5789:* "d4init.c/usr/src/bs/BUILD/glibc-2.1.92/csu/gcc2_compiled.int:t(0,1)=r(0,1);-2147483648;2147483647;char:t(0,2)=r(0,2);0;127;long int:t(0,3)=r(0,3);-2147483648;2147483647;unsigned int:t(0,4)=r(0,4);0000000000000;0037777777777;long unsigned int:t(0,5)=r(0,5);0000000000000;0037777777777;long long int:t(0,6)=@s64;r(0,6);01000000000000000000000;0777777777777777777777;long long unsigned int:t(0,7)=@s64;r(0,7);0000000000000;01777777777777777777777;short int:t(0,8)=@s16;r(0,8);-32768;32767;short unsigned int:t(0,9)=@s16;r(0,9);0;65535;signed char:t(0,10)=@s8;r(0,10);-128;127;unsigned char:t(0,11)=@s8;r(0,11);0;255;float:t(0,12)=r(0,1);4;0;double:t(0,13)=r(0,1);8;0;long double:t(0,14)=r(0,1);12;0;complex int:t(0,15)=s8real:(0,1),0,32;imag:(0,1),32,32;;complex float:t(0,16)=r(0,16);8;0;complex double:t(0,17)=r(0,17);16;0;complex long double:t(0,18)=r(0,18);24;0;__builtin_va_list:t(0,19)=*(0,20)=(0,20)../include/libc-symbols.h../sysdeps/unix/sysv/linux/_G_config.h../sysdeps/unix/sysv/linux/bits/types.h../include/features.h../include/sys/cdefs.h/usr/lib/gcc-lib/i386-redhat-linux/2.96/include/stddef.hsize_t:t(6,1)=(0,4)__u_char:t(3,1)=(0,11)__u_short:t(3,2)=(0,9)__u_int:t(3,3)=(0,4)__u_long:t(3,4)=(0,5)__u_quad_t:t(3,5)=(0,7)__quad_t:t(3,6)=(0,6)__int8_t:t(3,7)=(0,10)__uint8_t:t(3,8)=(0,11)__int16_t:t(3,9)=(0,8)__uint16_t:t(3,10)=(0,9)__int32_t:t(3,11)=(0,1)__uint32_t:t(3,12)=(0,4)__int64_t:t(3,13)=(0,6)__uint64_t:t(3,14)=(0,7)__qaddr_t:t(3,15)=(3,16)=*(3,6)__dev_t:t(3,17)=(3,5)__uid_t:t(3,18)=(3,3)__gid_t:t(3,19)=(3,3)__ino_t:t(3,20)=(3,4)__mode_t:t(3,21)=(3,3)__nlink_t:t(3,22)=(3,3)__off_t:t(3,23)=(0,3)__loff_t:t(3,24)=(3,6)__pid_t:t(3,25)=(0,1)__ssize_t:t(3,26)=(0,1)__rlim_t:t(3,27)=(3,4)__rlim64_t:t(3,28)=(3,5)__id_t:t(3,29)=(3,3)__fsid_t:t(3,30)=(3,31)=s8__val:(3,32)=ar(3,33)=r(3,33);0000000000000;0037777777777;;0;1;(0,1),0,64;;__daddr_t:t(3,34)=(0,1)__caddr_t:t(3,35)=(3,36)=*(0,2)__time_t:t(3,37)=(0,3)__useconds_t:t(3,38)=(0,4)__suseconds_t:t(3,39)=(0,3)__swblk_t:t(3,40)=(0,3)__clock_t:t(3,41)=(0,3)__clockid_t:t(3,42)=(0,1)__timer_t:t(3,43)=(0,1)__fd_mask:t(3,44)=(0,5)__fd_set:t(3,45)=(3,46)=s128fds_bits:(3,47)=ar(3,33);0;31;(3,44),0,1024;;__key_t:t(3,48)=(0,1)__ipc_pid_t:t(3,49)=(0,9)__blksize_t:t(3,50)=(0,3)__blkcnt_t:t(3,51)=(0,3)__blkcnt64_t:t(3,52)=(3,6)__fsblkcnt_t:t(3,53)=(3,4)__fsblkcnt64_t:t(3,54)=(3,5)__fsfilcnt_t:t(3,55)=(3,4)__fsfilcnt64_t:t(3,56)=(3,5)__ino64_t:t(3,57)=(3,5)__off64_t:t(3,58)=(3,24)__t_scalar_t:t(3,59)=(0,3)__t_uscalar_t:t(3,60)=(0,5)__intptr_t:t(3,61)=(0,1)__socklen_t:t(3,62)=(0,4)../linuxthreads/sysdeps/pthread/bits/pthreadtypes.h../sysdeps/unix/sysv/linux/bits/sched.h__sched_param:T(8,1)=s4sched_priority:(0,1),0,32;;_pthread_fastlock:T(7,1)=s8__status:(0,3),0,32;__spinlock:(0,1),32,32;;_pthread_descr:t(7,2)=(7,3)=*(7,4)=xs_pthread_descr_struct:pthread_attr_t:t(7,5)=(7,6)=s36__detachstate:(0,1),0,32;__schedpolicy:(0,1),32,32;__schedparam:(8,1),64,32;__inheritsched:(0,1),96,32;__scope:(0,1),128,32;__guardsize:(6,1),160,32;__stackaddr_set:(0,1),192,32;__stackaddr:(0,19),224,32;__stacksize:(6,1),256,32;;pthread_cond_t:t(7,7)=(7,8)=s12__c_lock:(7,1),0,64;__c_waiting:(7,2),64,32;;pthread_condattr_t:t(7,9)=(7,10)=s4__dummy:(0,1),0,32;;pthread_key_t:t(7,11)=(0,4)pthread_mutex_t:t(7,12)=(7,13)=s24__m_reserved:(0,1),0,32;__m_count:(0,1),32,32;__m_owner:(7,2),64,32;__m_kind:(0,1),96,32;__m_lock:(7,1),128,64;;pthread_mutexattr_t:t(7,14)=(7,15)=s4__mutexkind:(0,1),0,32;;pthread_once_t:t(7,16)=(0,1)_pthread_rwlock_t:T(7,17)=s32__rw_lock:(7,1),0,64;__rw_readers:(0,1),64,32;__rw_writer:(7,2),96,32;__rw_read_waiting:(7,2),128,32;__rw_write_waiting:(7,2),160,32;__rw_kind:(0,1),192,32;__rw_pshared:(0,1),224,32;;pthread_rwlock_t:t(7,18)=(7,17)pthread_rwlockattr_t:t(7,19)=(7,20)=s8__lockkind:(0,1),0,32;__pshared:(0,1),32,32;;pthread_spinlock_t:t(7,21)=(0,1)pthread_barrier_t:t(7,22)=(7,23)=s20__ba_lock:(7,1),0,64;__ba_required:(0,1),64,32;__ba_present:(0,1),96,32;__ba_waiting:(7,2),128,32;;pthread_barrierattr_t:t(7,24)=(7,25)=s4__pshared:(0,1),0,32;;pthread_t:t(7,26)=(0,5)wchar_t:t(9,1)=(0,3)wint_t:t(9,2)=(0,4)../include/wchar.h../wcsmbs/wchar.h__mbstate_t:t(11,1)=(11,2)=s8__count:(0,1),0,32;__value:(11,3)=u4__wch:(9,2),0,32;__wchb:(11,4)=ar(3,33);0;3;(0,2),0,32;;,32,32;;_G_fpos_t:t(2,1)=(2,2)=s12__pos:(3,23),0,32;__state:(11,1),32,64;;_G_fpos64_t:t(2,3)=(2,4)=s16__pos:(3,58),0,64;__state:(11,1),64,64;;../include/gconv.h../iconv/gconv.h :T(13,1)=e__GCONV_OK:0,__GCONV_NOCONV:1,__GCONV_NODB:2,__GCONV_NOMEM:3,__GCONV_EMPTY_INPUT:4,__GCONV_FULL_OUTPUT:5,__GCONV_ILLEGAL_INPUT:6,__GCONV_INCOMPLETE_INPUT:7,__GCONV_ILLEGAL_DESCRIPTOR:8,__GCONV_INTERNAL_ERROR:9,; :T(13,2)=e__GCONV_IS_LAST:1,__GCONV_IGNORE_ERRORS:2,;__gconv_fct:t(13,3)=(13,4)=*(13,5)=f(0,1)__gconv_init_fct:t(13,6)=(13,7)=*(13,8)=f(0,1)__gconv_end_fct:t(13,9)=(13,10)=*(13,11)=f(0,20)__gconv_trans_fct:t(13,12)=(13,13)=*(13,14)=f(0,1)__gconv_trans_context_fct:t(13,15)=(13,16)=*(13,17)=f(0,1)__gconv_trans_query_fct:t(13,18)=(13,19)=*(13,20)=f(0,1)__gconv_trans_init_fct:t(13,21)=(13,22)=*(13,23)=f(0,1)__gconv_trans_end_fct:t(13,24)=(13,25)=*(13,26)=f(0,20)__gconv_trans_data:T(13,27)=s20__trans_fct:(13,12),0,32;__trans_context_fct:(13,15),32,32;__trans_end_fct:(13,24),64,32;__data:(0,19),96,32;__next:(13,28)=*(13,27),128,32;;__gconv_step:T(13,29)=s56__shlib_handle:(13,30)=*(13,31)=xs__gconv_loaded_object:,0,32;__modname:(13,32)=*(0,2),32,32;__counter:(0,1),64,32;__from_name:(13,32),96,32;__to_name:(13,32),128,32;__fct:(13,3),160,32;__init_fct:(13,6),192,32;__end_fct:(13,9),224,32;__min_needed_from:(0,1),256,32;__max_needed_from:(0,1),288,32;__min_needed_to:(0,1),320,32;__max_needed_to:(0,1),352,32;__stateful:(0,1),384,32;__data:(0,19),416,32;;__gconv_step_data:T(13,33)=s36__outbuf:(13,34)=*(0,11),0,32;__outbufend:(13,34),32,32;__flags:(0,1),64,32;__invocation_counter:(0,1),96,32;__internal_use:(0,1),128,32;__statep:(13,35)=*(11,1),160,32;__state:(11,1),192,64;__trans:(13,28),256,32;;__gconv_info:T(13,36)=s8__nsteps:(6,1),0,32;__steps:(13,37)=*(13,29),32,32;__data:(13,38)=ar(3,33);0;-1;(13,33),64,0;;__gconv_t:t(13,39)=(13,40)=*(13,36)_G_iconv_t:t(2,5)=(2,6)=u44__cd:(13,36),0,64;__combined:(2,7)=s44__cd:(13,36),0,64;__data:(13,33),64,288;;,0,352;;_G_int16_t:t(2,8)=(0,8)_G_int32_t:t(2,9)=(0,1)_G_uint16_t:t(2,10)=(0,9)_G_uint32_t:t(2,11)=(0,4)_IO_stdin_used:G(0,1)GCC: (GNU) 2.96 20000731 (experimental)GCC: (GNU) 2.96 20000731 (experimental)GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 3.0.1GCC: (GNU) 2.96 20000731 (experimental)01.0101.0101.01.symtab.strtab.shstrtab.interp.note.ABI-tag.hash.dynsym.dynstr.gnu.version.gnu.version_r.rel.got.rel.bss.rel.plt.init.plt.text.fini.rodata.data.eh_frame.ctors.dtors.got.dynamic.sbss.bss.stab.stabstr.comment.note# 1((7 ?88Go>>rTo`c  l  u 00  ~ / ,, ``  `.`8 00001(2@@2@  @  `@O<+P.] H((8> 0    ,``.00001(2@2 4 "-h.10?L2K@ a0t P2  l.0"Њ 0  000 ,   &-5>I2Q2Yh2d2r22$4(4,4.@4@5@IDI!+p 0@s C PP: a q+ y x `J P 0- -B k @ @P  x| &9w 7@r F U@4 e^ l}} } `. .@!  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initfini.cgcc2_compiled.init.ccrtstuff.cp.0__DTOR_LIST__completed.1__do_global_dtors_aux__EH_FRAME_BEGIN__fini_dummyobject.2frame_dummyinit_dummyforce_to_data__CTOR_LIST____do_global_ctors_aux__CTOR_END____DTOR_END____FRAME_END__routine.cplace.ccell.cmodel.cnet.crow.ctwio.cyalio.cfileio.clefdefio.clexpanddexpandcurr_key.0read_status.1read_direction.2names.crandom.cxj_ptrk_ptrcmisc.chook_fntstr.0tran.cpad.cbookshelf.cstFiletiming.cpath.cdp.cdpfun.crcong.c_unit_vc_unit_hcbalance.cbin.cdpcheck.cinfoPrintGPInformationWriteDEFFileNetlistSecondMaxBookSetChipSizeNetNamePermutationEndBinAddCellWithoutChangeXYResnapCongestionReportResetTimerPinGraphInitSingleSourcePrintOverflowInitStandardRowsGreedyImproveHashInitializeBinStructureBinViolateAmountBinAdjustToRowNetCongestTypeSetCellRowByBinnOuterNumTerminalsSaveNetBinRefreshSortByGainYbLastWriteUnitCongestionFreeTimingMemoryCongGenCellMoveLogTwoBinSwapCellEXPANDReadLefFileBinExchangeCellInitEdgeBlockIdentifyLongestNetsReadPlaceFileCheckCellAbutRowNumByYmy_srand48NetFirstPinelapsed_timeSingleCellTendencyGeneratePadFilestrchr@@GLIBC_2.0sh_try_numaccept_numlnumExtractPinNameNumTermInBingetcoreCreateRoutingFileMinPrintTimerSetXAccordingSequence__ctype_tolower@@GLIBC_2.0CheckPlacedPrintLongestPathAnalyzeArgumentsgzopenPrintTempInfoPadInterconnectionReadLEFDEFFormatBookWritePlaceFileDeleteDangleStuffs_DYNAMICSpreadCellsAtCenterGenerateModulesReadPinNetNameToNumberDistancePlatformInfo_currEdgeBlkUpdateTempMPINPinNoResetAllPinOffsetFreeExpansionMemoryCalculateCenterPinWirelengthfOpenLogFileOutputDEFComponentsWritePadLocationsfake_stepYalReadIOlist__register_frame_info@@GLIBC_2.0ReadBoundaryCreateBinExternalNetssw_accept_numReadModelPinmystrduplast_gainlocaltime@@GLIBC_2.0DeleteLargeCellsFanoutFirstPincircuitnQTailMaxTopoListNextNetSuccPinWhichInstancestrcmp@@GLIBC_2.0BinExternalNetsMDELAYCheckCompareBinXYReadUnitCongestionAreaCongestionCostCurrentNumberOfCellsToMove_fp_hwReadCellDelayWriteLogFileHeadTimingViolationOutputDEFPadsCongMakeMoveFirstNonemptyCharReadCongestionFromRyanCompareCellWidthfprintf@@GLIBC_2.0MovingProfitmyrandverboseCloseLogFileMPINInputPinNofflush@@GLIBC_2.0CheckOverlapMPINOutputPinNoResolveOverlapTimingGreedySwitchfLogfileMPINCapaResiPinXYAssignCellPositionByChainNetNextPinMoveCellsFromBinByMovingNetSingleCellGreedyImproveModifyChainYalIsCommentStartCongestionByNetRoutingEstModel2SaveLongestPathAnnealingShiftnetSetModelParametersReadDefFilePrintMaxRowLengthBinPenaltyAmountSetPinOffset_namebuffAcceptNewRandomSortnMemMdelayIdentifyCellsToMoveFourBinOptimization_block_index__dso_handleOutputDEFNetsinitial_bbfl_accept_numLinkDelaysToCellsRestoreAllPinOffsetIsLargeCellCheckPadWidthAssignPadLocationsSetBadCellsSetBinCellsReadWeightsFileextractlReadNetsFileputchar@@GLIBC_2.0DefReadPinsInitRowChaingetpwuid@@GLIBC_2.0fBB_resolveBoundingBoxTagChangePrintCellWidthPutPadFrozennPinWriteOneLineLocalImprovePlacementCreateCongestionMapMoveCellToOtherRowAlleviateCongestionYalReadDimensionmodelfTotalWBBCongestionCostCurrentReadSdfFileReadRowFromPARCreateMovementDisplayFileReadRowFromGDPGreedySwitchWhichCellObtainDesignNameWriteLayoutFileFindProperResolution_pathLastNonemptyCharsystem@@GLIBC_2.0FormulateCPLEXFileAcceptSingleCellMoveLefSetChipSizechmod@@GLIBC_2.0ReduceLongestNetlengthnMdlCreateYalFilesPinGraphRelaxPinGraphDFSLEFDEFCheckRowsrandom@@GLIBC_2.0WriteNewDefFileReadStatisticsFileputs@@GLIBC_2.0nLineCounter_initOutputPinDelayBinInitialRowNumberPrintBinLengthSortCellForEachRownLoopSortPinsByCellargInBinBoxCompareCellAdjustVerticalPadsmalloc@@GLIBC_2.0PrintBinCongestionPadsMaxXEstimateCongestionByBBstdrowCheckRowOverflowMoveNetFromBinpinnameSetPinfscanf@@GLIBC_2.0SwitchCellAtOneRowBuildNetToPathMappingMPINPointerWeightedBoundingBoxChangeReportCellDistanceMDELAYPointerCloseCellSwitchWeightedSingleCellGreedyImprove__register_frame_info_basesCellStatistics__deregister_frame_info@@GLIBC_2.0IdentifyMultiCongestedAreasSnapCellsIntoBinsTopoListAddPinExpansionBasedOnLPOutputGCFFilerint@@GLIBC_2.0ReadNumberReadModelIsValidPrintRowLengthFastGreedyImproveCPLEXOptimizeCellNetsSwitchAlleviateCongCountNameMemorystdout@@GLIBC_2.0stderr@@GLIBC_2.0IsStandardCellCalculateCellMovementCongAcceptMoveReadAuxilaryFilenet_tagabort@@GLIBC_2.0IdentifyCongestedBinsScaleCellSizeSetExpansionForAreasSMBinBalanceMPINCheckFreeRoutingMemoryTotalChipCongestionReadPairDetermineExpansionMethodCalculateAllFanOutDelaysCompareCellByTendReadRowInfoNewNamenIterCountPinNumChooseMovingCandidatesSetCellAtBinCenterChangeNetlistUpdateEdgeTimingDelayvfprintf@@GLIBC_2.0PermutationSpreadFindLongestPathGenerateNetlistsfatalFindOneCongestedAreafseek@@GLIBC_2.0PrepareRowLengthPrintPadForYalChooseCellFromNetBinExternalStatsReadPadLocationsNormalizedWirelengthtime@@GLIBC_2.0IsVerticalPadSetPinModelPinCongestionChangeByNet_startNColor__deregister_frame_info_basesTrySingleCellMovelog_base2YalReadNetworkSetCellInitialPlaceIdentifyCongestedNetsNetAddPinfgets@@GLIBC_2.0OutputRoutingInputFileGDIFIsEmptyQueueSetBinCenterSortAllCellsNewEdgeVectorSwapMoveSingleCellReachBalanceRandomInitAccuratePreDPProcessExpandAreaPadDistanceNetSegmentDelayPrintModuleForyalfputs@@GLIBC_2.0nClstrstr@@GLIBC_2.0strlen@@GLIBC_2.0PinOffsetByDirResetCongestedAreaWriteLEFFileRandomStringFilterEstimationProfitPinGraphBuildInBinBoxXYAlleviateCongestionInDPpanicRestoreOlduname@@GLIBC_2.0qsort@@GLIBC_2.0NetInitPinmystricmpnNetPinTypeStringCellGainRowGreedySwitchSingleCellGreedySetYOffsetTestWireDelayDisplaySingleNetRouteIsLongNetTimingIssuesGetCongestedAreaWhichPadDPUsageRowAdjustBinfTotalBBReadPinWithoutNameCreateBinWireFile_block_offsetstrncmp@@GLIBC_2.0FaninPinModelTypeStringWriteNetsFileInCongAreaWriteBookshelfFormatnMdelayYalReadModelType_numEdgeBlkReadAllCellfputc@@GLIBC_2.0ShiftCellToOtherRowmystrrchrWhichPinNoWhichPinGenMoveDirReadLayoutFileCircuitStatisticsmysrandmy_lrand48PrintModulesWithPinLocationDeleteDuplicate__bss_startBuildDoubleChainInitializeRowLengthCalculateTotalTimingViolationModifyChainShiftOutputCellDistributionmaingzcloseExpandCongestedAreaInitTimingParametersBinAddCellCheckCellRowDirectionStringCalculateAllPathsWhichNetSnapCellsIntoBinsKeepSeqGenerateGDPFileInitHashYalReadModelNameMPINGateDelay__libc_start_main@@GLIBC_2.0ColumnAdjustBinIncreaseUnBalanceReadNetlistInformationFreeNameBufferPrintWirelengthDistributionSetCellRowNumberBoundingBoxTagChangeFastArrayAddexp@@GLIBC_2.0LefCheckModelsPadsMinXqueueyFreeEdgeBlockBinChangeCellOrderCompareCell1WriteRunningTimePreReadLefFilenMpinCalculateBinCongestionstrcat@@GLIBC_2.0TopoListInitdata_startModifyRowLengthDefReadCellasctime@@GLIBC_2.0CurrentTimeReadConfigFilePreDPProcessLEFDEFLongestPathcolorprintf@@GLIBC_2.0ReadWhiteSpaceFile_pathEdgeMemgetuid@@GLIBC_2.0_finiTimingRowGreedySwitchRearrangePadsReportLongestPathCheckRowForDPSetPadRangeLefReadPinFreeBinMemoryMDELAYPointerByPinQueueOutIsMoveTruelyReduceWLWriteWeightsFilenMemMpinBinCellsOutputbinfclose@@GLIBC_2.1BookChangeRowSpacingkbSaveCellOldLocationstrrchr@@GLIBC_2.0times@@GLIBC_2.0WriteAuxilaryFileLDEFPadDirectionReversePureStandardNetSaveDeltaDensityDensityConstraintMoveCellsFromBinRowLengthSetAverageCongestioncellCalculateAllWireDelays__cxa_finalize@@GLIBC_2.1.3FreeAllocatedMemoryAnnealingSwitchBoundingBoxUpdatePinGraphDFS_visitFreeBinExternalNetsCachegethostname@@GLIBC_2.0ShortestRowLengthDuplicateBinFreeRowMemorySetCellModelDeleteLargeCellsForYalPrintCongestionDistributionReadTWFormatReadYalCtlFileBinDelCellBinFindTailModelPinLEFDEFGateDelayLEFDEFTimingInitNetBoundingBoxRefreshstepSpreadCellsIsMoveReduceWLAllocateBinMemoryDegradeRowBalancePrintPinInformationCalculateWirelengthUpdateCellPositionsw_try_numexit@@GLIBC_2.0info1SaveCongestedAreaBinPrintCellUserInfocalloc@@GLIBC_2.0CheckCellsInRowIsSameModuleLinkPinsToCellsSetChipSizeSMRowBalancePinTypeCongestionToColorWriteWhiteSpaceFileYalIsCommentEndsscanf@@GLIBC_2.0_edataCongestionModelPadDistanceAndBoundaryReadModelDelay_GLOBAL_OFFSET_TABLE_free@@GLIBC_2.0_endDuplicateTermqueuexlong_netReportPath_currEdgeOffModifyChainOfTwoRowCalculateCellTendencyBookReadPlaceFileAreaEstTotalCongestionstrncasecmp@@GLIBC_2.0CostAllocateExpansionMemoryPinCapaResiReadYalFormatIdentifyInternalNetsQueueInitWriteFileTitleReadTimingConstraintsRejectSingleCellMoveCongestionCostRefreshGreedyFlippingSetCellCordinatesPinGraphTopologicalSortReadBookshelfFormatMarkCongestedAreasSetDefUnitNetPinBinCongestionPriorFanoutNextPinpinFileNamenCdelayfopen@@GLIBC_2.1IsLargeModelNextNonemptyCharIncreasingTimingPrepareRowBalanceCheckPrintExpansionMethodbPadDeterminedTotalRegionCongestionCalculateWeightedWirelengthBoundingBoxChangeRoutingCongestionAnalysism_pinModelType_IO_stdin_usedWriteConstraintsFilePinNameCongRestoreMoveReadCPLEXSolutionCellDirectionfatal_hookCreateDisplayFileReadCircuitQueueEnterIsPrimaryInsrandom@@GLIBC_2.0RowViolateAmountReadDieDimensionAnalyzeCongestedAreasPrintCongestedAreaReadNodesFilesh_accept_numTopoListFirstWriteNodesFileNetBinRefreshTagCreatePlacementFileReadExistingNetlistDynamicAllocateModelPinsCompareCellByXChangeDividerCongestionCost_timersprintf@@GLIBC_2.0ReadRoutedPathfwrite@@GLIBC_2.0Random01AssignWeightAlongLongestPath__data_startPrepareBinBalanceCheckCheckDelays_rcongwarnAdjustRightPadsDefReadPadSwapIntPtrnQNumPrintNetlistInformationm_delayRoutingEstModel1TopologicalSwitchComparePinCreateTwoModelsNumTerminalsIdentifyCongestedAreaInitTimingForPartitioningcdelay_edgeBlockIsStandardCellPtrBoundingBoxReadCongestionFromMGCreateNewPathCreateScriptFileLongNetChooseCellPairBuildBinExternalNetsCacheCheckDetailPlacementViolationInitNameBufferResetNetTagPrintRowLengthForBinsInitCellDelaysReadYalFileGateDelayPinPairDelaySetBinGridnQHead__gmon_start__LDEFPadDirectionDateInfostrcpy@@GLIBC_2.0nStdAnalyzeRoutedPath